<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/imx6sl-clock.h, branch linux-4.15.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.15.y</id>
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<updated>2015-10-12T13:55:59Z</updated>
<entry>
<title>clk: imx6: Add SPDIF_GCLK clock in clock tree</title>
<updated>2015-10-12T13:55:59Z</updated>
<author>
<name>Shengjiu Wang</name>
<email>shengjiu.wang@freescale.com</email>
</author>
<published>2015-10-10T10:15:06Z</published>
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<id>urn:sha1:84a87250ee4e4f7cf5865be9757e2ea758e5cae3</id>
<content type='text'>
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.

We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.

So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.

Signed-off-by: Shengjiu Wang &lt;shengjiu.wang@freescale.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: clk-imx6sl: refine clock tree for SSI</title>
<updated>2014-09-16T02:09:39Z</updated>
<author>
<name>Shengjiu Wang</name>
<email>shengjiu.wang@freescale.com</email>
</author>
<published>2014-09-09T09:13:25Z</published>
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<id>urn:sha1:dbaf381ffbf3acd4ac9a987f567a2b1a5edf6e62</id>
<content type='text'>
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.

Signed-off-by: Shengjiu Wang &lt;shengjiu.wang@freescale.com&gt;
Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
</content>
</entry>
<entry>
<title>ARM: imx6sl: add BYPASS support for PLL clocks</title>
<updated>2014-09-16T02:06:48Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@freescale.com</email>
</author>
<published>2014-09-01T06:29:53Z</published>
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<id>urn:sha1:e90f41990dce3557e345410ef33b0a47e8cb49fc</id>
<content type='text'>
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q.  The difference is that only anaclk1
is available on imx6sl.

Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
</content>
</entry>
<entry>
<title>ARM: imx6sl: add missing enet clock for imx6sl</title>
<updated>2014-06-17T13:11:18Z</updated>
<author>
<name>Fugang Duan</name>
<email>b38611@freescale.com</email>
</author>
<published>2014-05-19T07:46:41Z</published>
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<id>urn:sha1:4ca2ad55553ef528c055761a9fa4d2c140f7318b</id>
<content type='text'>
There's a enet clock gate missing in clock tree, thus add it.

Signed-off-by: Fugang Duan &lt;B38611@freescale.com&gt;
Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
</content>
</entry>
<entry>
<title>ARM: imx6sl: Add missing spba clock to clock tree</title>
<updated>2013-12-31T01:36:37Z</updated>
<author>
<name>Nicolin Chen</name>
<email>Guangyu.Chen@freescale.com</email>
</author>
<published>2013-12-13T15:44:08Z</published>
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<id>urn:sha1:8962a5dbe0a5faa14c075b1c652b1ec6d9810e53</id>
<content type='text'>
We are missing spba clock in imx6sl's clock tree, thus add it.

Signed-off-by: Nicolin Chen &lt;Guangyu.Chen@freescale.com&gt;
Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: imx6sl: Add missing pll4_audio_div to the clock tree</title>
<updated>2013-12-31T01:36:36Z</updated>
<author>
<name>Nicolin Chen</name>
<email>Guangyu.Chen@freescale.com</email>
</author>
<published>2013-12-13T15:44:07Z</published>
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<id>urn:sha1:238fb1821439b907715a38f38edaae31182b5daf</id>
<content type='text'>
There's a dividor for pll4_audio clock missing in clock tree, thus add it.

Signed-off-by: Nicolin Chen &lt;Guangyu.Chen@freescale.com&gt;
Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END</title>
<updated>2013-12-31T01:36:23Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@linaro.org</email>
</author>
<published>2013-11-16T14:33:16Z</published>
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<id>urn:sha1:4e5d0d61846a752e9fff0ee8cc8aab372e1fe3a3</id>
<content type='text'>
The macro name IMX6SL_CLK_CLK_END is a little insane.  Rename it to
IMX6SL_CLK_END.

Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: imx: add clock support for imx6sl</title>
<updated>2013-06-17T07:45:11Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@linaro.org</email>
</author>
<published>2013-05-03T03:06:46Z</published>
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<id>urn:sha1:45fe6810347b0a83561a13d9ee656c899a309fc0</id>
<content type='text'>
Add clock support for i.MX6 SoloLite.  It uses the dtc marco support to
define all clock IDs in imx6sl-clock.h, which will be included by both
clock driver and device tree sources, so that the data will stay sync
all the time between kernel and DT.

Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
</feed>
