<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/histb-clock.h, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-05-15T22:12:06Z</updated>
<entry>
<title>clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC</title>
<updated>2018-05-15T22:12:06Z</updated>
<author>
<name>Jianguo Sun</name>
<email>sunjianguo1@huawei.com</email>
</author>
<published>2018-05-04T08:56:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=80820a7bc8eb92bee8dab36668dfc567062b0ccf'/>
<id>urn:sha1:80820a7bc8eb92bee8dab36668dfc567062b0ccf</id>
<content type='text'>
There are two USB3 host controllers on Hi3798CV200 SoC.
This commit adds missing clocks for them.

Signed-off-by: Jianguo Sun &lt;sunjianguo1@huawei.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: hi3798cv200: add COMBPHY0 clock support</title>
<updated>2018-02-27T01:19:12Z</updated>
<author>
<name>Jianguo Sun</name>
<email>sunjianguo1@huawei.com</email>
</author>
<published>2018-01-24T11:48:27Z</published>
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<id>urn:sha1:80f8ce589517c478abdae07a758b37b362886cb2</id>
<content type='text'>
The clock COMBPHY1 has already been supported by hi3798cv200 driver,
but COMBPHY0 is missing.  It adds COMBPHY0 clock support.

Since the mux table is being shared by COMBPHY0 and COMBPHY1, it renames
comphy1_mux_p and comphy1_mux_table a bit to drop instance number '1'
from there.

Signed-off-by: Jianguo Sun &lt;sunjianguo1@huawei.com&gt;
Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: hi3798cv200: fix define indentation</title>
<updated>2018-02-27T01:19:12Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@linaro.org</email>
</author>
<published>2018-01-24T11:48:26Z</published>
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<id>urn:sha1:a44d1f531a39da8cd6497372e713f5998b2d67af</id>
<content type='text'>
It's a coding-style fix, which corrects the indentation for all those
clock definitions, so that the code looks nicer and new definitions can
be added with a recommended indentation.

Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: hisilicon: add usb2 clocks for hi3798cv200 SoC</title>
<updated>2017-06-21T17:46:45Z</updated>
<author>
<name>Jiancheng Xue</name>
<email>xuejiancheng@hisilicon.com</email>
</author>
<published>2017-06-21T09:00:41Z</published>
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<id>urn:sha1:0d84659619696b42417c0d6c2eb7661a3ce254c0</id>
<content type='text'>
Add usb2 clocks for hi3798cv200 SoC.

Signed-off-by: Jiancheng Xue &lt;xuejiancheng@hisilicon.com&gt;
Reviewed-by: Daniel Thompson &lt;daniel.thompson@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: hisilicon: add CRG driver for Hi3798CV200 SoC</title>
<updated>2016-11-11T23:43:49Z</updated>
<author>
<name>Jiancheng Xue</name>
<email>xuejiancheng@hisilicon.com</email>
</author>
<published>2016-10-29T06:13:37Z</published>
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<id>urn:sha1:707d33cb0b731472b7564d9fad8d45cbbd7fece3</id>
<content type='text'>
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.

Signed-off-by: Jiancheng Xue &lt;xuejiancheng@hisilicon.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
