kernel/include/dt-bindings/clock/g12a-clkc.h, branch linux-6.2.y

dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings

2020-11-26T14:23:34Z

This adds the MIPI DSI Host Pixel Clock bindings. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20201126141600.2084586-2-narmstrong@baylibre.com

dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs

2020-06-19T15:16:09Z

This adds the Neural Network Accelerator IP source clocks. Signed-off-by: Dmitry Shmidt Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200610083012.5024-2-narmstrong@baylibre.com

dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs

2020-02-19T17:40:00Z

Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet

dt-bindings: clk: meson: add sm1 periph clock controller bindings

2019-08-26T09:00:15Z

Update the documentation to support clock driver for the Amlogic SM1 SoC and expose the GP1, DSU and the CPU 1, 2 & 3 clocks. SM1 clock tree is very close, the main differences are : - each CPU core can achieve a different frequency, albeit a common PLL - a similar tree as the clock tree has been added for the DynamIQ Shared Unit - has a new GP1 PLL used for the DynamIQ Shared Unit - SM1 has additional clocks like for CSI, NanoQ an other components Signed-off-by: Neil Armstrong Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet

clk: meson: g12a: expose CPUB clock ID for G12B

2019-08-09T10:12:37Z

Expose the CPUB clock id to add DVFS to the second CPU cluster of the Amlogic G12B SoC. Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet

Merge branch 'v5.3/dt' into v5.3/drivers

2019-06-11T09:20:28Z

dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs

2019-06-11T09:15:57Z

Add clock ids used by the temperature sensors of the G12A Socs Reviewed-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Guillaume La Roque Signed-off-by: Jerome Brunet [fixed commit message]

clk: meson: fix MPLL 50M binding id typo

2019-05-20T10:05:46Z

MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number) Fix this before it gets used. Fixes: 25db146aa726 ("dt-bindings: clk: meson: add g12a periph clock controller bindings") Reported-by: Martin Blumenstingl Acked-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Jerome Brunet

dt-bindings: clk: g12a-clkc: add VDEC clock IDs

2019-04-01T08:45:11Z

Expose the three clocks related to the video decoder. Signed-off-by: Maxime Jourdan Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com

dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID

2019-03-19T20:11:25Z

Add a clock ID for the reference clock feeding the USB3+PCIe Combo PHY. Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190307141455.23879-3-narmstrong@baylibre.com