<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/exynos7-clk.h, branch linux-4.15.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.15.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.15.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2015-09-15T09:18:15Z</updated>
<entry>
<title>clk: samsung: exynos7: Add required clock tree for UFS</title>
<updated>2015-09-15T09:18:15Z</updated>
<author>
<name>Alim Akhtar</name>
<email>alim.akhtar@samsung.com</email>
</author>
<published>2015-09-10T08:44:37Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7993b3ebec979b23c2d7425959c9d232c452498b'/>
<id>urn:sha1:7993b3ebec979b23c2d7425959c9d232c452498b</id>
<content type='text'>
Adding required mux/div/gate clocks for UFS controller
present on Exynos7.

Signed-off-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: Correct CMU_FSYS1 clocks names</title>
<updated>2015-09-15T09:16:10Z</updated>
<author>
<name>Alim Akhtar</name>
<email>alim.akhtar@samsung.com</email>
</author>
<published>2015-09-10T08:44:35Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=753195a749a6c849dbd05cb82a2deb4190a06257'/>
<id>urn:sha1:753195a749a6c849dbd05cb82a2deb4190a06257</id>
<content type='text'>
This patch renames CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.

Signed-off-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: Correct CMU_FSYS0 clocks names</title>
<updated>2015-09-15T09:16:09Z</updated>
<author>
<name>Alim Akhtar</name>
<email>alim.akhtar@samsung.com</email>
</author>
<published>2015-09-10T08:44:34Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a259a61be1d0d01aa2dd4778722e4d161780c813'/>
<id>urn:sha1:a259a61be1d0d01aa2dd4778722e4d161780c813</id>
<content type='text'>
This patch renames CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.

Signed-off-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: Correct CMU_PERIC1 clocks names</title>
<updated>2015-09-15T09:16:07Z</updated>
<author>
<name>Alim Akhtar</name>
<email>alim.akhtar@samsung.com</email>
</author>
<published>2015-09-10T08:44:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=33b8b739ef5ec43b5119ab011c0a885fc565ad19'/>
<id>urn:sha1:33b8b739ef5ec43b5119ab011c0a885fc565ad19</id>
<content type='text'>
This patch renames CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.

Signed-off-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: Correct CMU_PERIC0 clocks names</title>
<updated>2015-09-15T09:16:07Z</updated>
<author>
<name>Alim Akhtar</name>
<email>alim.akhtar@samsung.com</email>
</author>
<published>2015-09-10T08:44:31Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3f54fb1e09da301173bc44845f93a1be7fe33d8f'/>
<id>urn:sha1:3f54fb1e09da301173bc44845f93a1be7fe33d8f</id>
<content type='text'>
This patch renames CMU_PERIC0 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric0_66.

Signed-off-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC</title>
<updated>2015-09-15T09:02:29Z</updated>
<author>
<name>Alim Akhtar</name>
<email>alim.akhtar@samsung.com</email>
</author>
<published>2015-09-10T08:44:27Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=2cbb51574557a8affe0732ad23a840cf90c656b1'/>
<id>urn:sha1:2cbb51574557a8affe0732ad23a840cf90c656b1</id>
<content type='text'>
This adds some of the missing GATE clocks of CMU_TOPC block.

Signed-off-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: add clocks for audio block</title>
<updated>2015-01-15T14:18:51Z</updated>
<author>
<name>Padmavathi Venna</name>
<email>padma.v@samsung.com</email>
</author>
<published>2015-01-13T11:27:42Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9f930a39e135d370d17e7a1ab73ddebcfb896f98'/>
<id>urn:sha1:9f930a39e135d370d17e7a1ab73ddebcfb896f98</id>
<content type='text'>
Add required clk support for I2S, PCM and SPDIF.

Signed-off-by: Padmavathi Venna &lt;padma.v@samsung.com&gt;
Reviewed-by: Vivek Gautam &lt;gautam.vivek@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: add clocks for SPI block</title>
<updated>2015-01-15T14:11:40Z</updated>
<author>
<name>Padmavathi Venna</name>
<email>padma.v@samsung.com</email>
</author>
<published>2015-01-13T11:27:41Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ee74b56ab2f72c088fc5a8ba3797ef6a452d692a'/>
<id>urn:sha1:ee74b56ab2f72c088fc5a8ba3797ef6a452d692a</id>
<content type='text'>
Add clock support for 5 SPI channels.

Signed-off-by: Padmavathi Venna &lt;padma.v@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: add gate clock for DMA block</title>
<updated>2015-01-15T14:11:40Z</updated>
<author>
<name>Padmavathi Venna</name>
<email>padma.v@samsung.com</email>
</author>
<published>2015-01-13T11:27:40Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9cc2a0c95ff3f815deeba1ccd0d11b1d3bc46551'/>
<id>urn:sha1:9cc2a0c95ff3f815deeba1ccd0d11b1d3bc46551</id>
<content type='text'>
Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna &lt;padma.v@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
<entry>
<title>clk: samsung: exynos7: Add required clock tree for USB</title>
<updated>2014-12-23T11:02:14Z</updated>
<author>
<name>Vivek Gautam</name>
<email>gautam.vivek@samsung.com</email>
</author>
<published>2014-11-21T13:35:51Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=83f191a7cdf5286a8f3745e847f50c29fa349da9'/>
<id>urn:sha1:83f191a7cdf5286a8f3745e847f50c29fa349da9</id>
<content type='text'>
Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.

Signed-off-by: Vivek Gautam &lt;gautam.vivek@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
</content>
</entry>
</feed>
