kernel/include/dt-bindings/clock/exynos5420.h, branch linux-5.11.y

clk: samsung: Add clk ID definitions for the CPU parent clocks

2020-09-17T10:05:15Z

Add clock ID definitions for the CPU parent clocks for SoCs which don't have such definitions yet. This will allow us to reference the parent clocks directly by cached struct clk_hw pointers in the clock provider, rather than doing clk lookup by name. Reviewed-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200826171529.23618-1-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki

clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d

2020-09-17T10:05:13Z

This patch adds ID for the mout_sw_aclk_g3d (SW_CLKMUX_ACLK_G3D) clock, mostly for internal use in the CMU driver. It will allow to avoid the __clk_lookup() call when setting up the clock during the clock provider initialization. Link: https://lore.kernel.org/r/20200811151251.31613-1-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki

clk: samsung: add needed IDs for DMC clocks in Exynos5420

2019-06-06T13:52:30Z

Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Acked-by: Rob Herring Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: Sylwester Nawrocki

dt-bindings: clock: samsung: Add SPDX license identifiers

2018-10-15T18:35:00Z

Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Reviewed-by: Rob Herring Signed-off-by: Rob Herring

clk: samsung: Add missing exynos5420 audio related clocks

2017-06-09T11:12:54Z

This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Tested-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki

clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)

2016-09-09T08:11:44Z

This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller) which generates clocks for DRAM and NoC (Network on Chip) busses. Signed-off-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki

dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC

2016-04-15T16:13:42Z

This patch adds the clock id for ACLK clock of Exynos542x SoC. ACLK clock means the source clock of AMBA AXI bus. This clock id should be used for Bus frequency scaling. Signed-off-by: Chanwoo Choi Tested-by: Markus Reichl Tested-by: Anand Moon Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki

clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock

2015-12-16T15:35:26Z

With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5420. Changes by Bartlomiej: - split Exynos5420 support from the original patches - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c Signed-off-by: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Sylwester Nawrocki

clk: samsung: exynos542x: add missing parent GSCL block clocks

2015-12-16T15:35:17Z

This patch adds clocks, which are required for preserving parent clock configuration on GSCL power domain on/off. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki

clk: exynos5420: Add IDs for clocks used in DISP1 power domain

2015-01-28T23:52:22Z

When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas Acked-by: Sylwester Nawrocki Acked-by: Michael Turquette Signed-off-by: Kukjin Kim