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<title>kernel/include/dt-bindings/clock/at91.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2024-12-17T08:10:21Z</updated>
<entry>
<title>dt-bindings: clock: Add SAMA7D65 PMC compatible string</title>
<updated>2024-12-17T08:10:21Z</updated>
<author>
<name>Dharma Balasubiramani</name>
<email>dharma.b@microchip.com</email>
</author>
<published>2024-12-06T19:59:52Z</published>
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<id>urn:sha1:1c9eb9e684c606982c5dba019c58eaed5474c3c0</id>
<content type='text'>
Add the `microchip,sama7d65-pmc` compatible string to the existing binding,
since the SAMA7D65 PMC shares the same properties and clock requirements
as the SAMA7G5.

Export MCK3 and MCK5 to be accessed and referenced in DT to assign to
the clocks property for sama7d65 SoC.

Signed-off-by: Dharma Balasubiramani &lt;dharma.b@microchip.com&gt;
Signed-off-by: Ryan Wanner &lt;Ryan.Wanner@microchip.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/5252a28531deaee67af1edd8e72d45ca57783464.1733505542.git.Ryan.Wanner@microchip.com
[claudiu.beznea: use tabs instead of spaces in
 include/dt-bindings/clock/at91.h]
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clk: at91: Add clock IDs for the slow clock controller</title>
<updated>2024-12-08T15:55:26Z</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@tuxon.dev</email>
</author>
<published>2024-08-26T17:31:14Z</published>
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<id>urn:sha1:d87daa18535d38385f1da460c557c004e0b66347</id>
<content type='text'>
Add clock IDs for the slow clock controller. Previously, raw numbers
were used (0 or 1) for clocks generated by the slow clock controller. This
leads to confusion and wrong IDs were used on few device trees. To avoid
this add macros.

Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20240826173116.3628337-2-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT</title>
<updated>2024-08-07T16:16:47Z</updated>
<author>
<name>Varshini Rajendran</name>
<email>varshini.rajendran@microchip.com</email>
</author>
<published>2024-07-29T07:08:03Z</published>
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<id>urn:sha1:3dc73106ffc47640e692b9b32ebfd59d776c07fd</id>
<content type='text'>
Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.

Signed-off-by: Varshini Rajendran &lt;varshini.rajendran@microchip.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Link: https://lore.kernel.org/r/20240729070803.1990916-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</content>
</entry>
<entry>
<title>clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT</title>
<updated>2022-01-25T01:05:45Z</updated>
<author>
<name>Tudor Ambarus</name>
<email>tudor.ambarus@microchip.com</email>
</author>
<published>2022-01-11T12:53:10Z</published>
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<id>urn:sha1:a5ab04af49434aef532bf6cd4baa08a13665d608</id>
<content type='text'>
MCK1 feeds the External Bus Interface (EBI). EBI's clock rate is used
to translate EBI's timmings to SMC timings, thus we need to handle MCK1
in the EBI driver. Allow MCK1 to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Link: https://lore.kernel.org/r/20220111125310.902856-1-tudor.ambarus@microchip.com
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT</title>
<updated>2022-01-25T01:05:34Z</updated>
<author>
<name>Zixun LI</name>
<email>admin@hifiphile.com</email>
</author>
<published>2022-01-11T14:20:50Z</published>
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<id>urn:sha1:ea2be22f3d37b1e77fbfe46cd6536eab667107ec</id>
<content type='text'>
Make AUDIOPINCK accessible via phandle to select it
as peripheral clock parent using assigned-clock-parents in DT
where available.

Signed-off-by: Zixun LI &lt;admin@hifiphile.com&gt;
Reviewed-by: Claudiu Beznea &lt;Claudiu.Beznea@microchip.com&gt;
Link: https://lore.kernel.org/r/20220111142051.37957-1-admin@hifiphile.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: at91: sama7g5: register cpu clock</title>
<updated>2020-12-19T19:50:56Z</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2020-11-19T15:43:17Z</published>
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<id>urn:sha1:91f3bf0d5315ea3f139ae440f2b7772ecdcd67ec</id>
<content type='text'>
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: at91: add sama7g5 pll defines</title>
<updated>2020-12-19T19:50:55Z</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@microchip.com</email>
</author>
<published>2020-11-19T15:43:08Z</published>
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<id>urn:sha1:3d86ee17d4670406d07f92da6fa4f2aa82cdc5a2</id>
<content type='text'>
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.

Suggested-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: at91: allow setting all PMC clock parents via DT</title>
<updated>2020-05-27T03:22:50Z</updated>
<author>
<name>Michał Mirosław</name>
<email>mirq-linux@rere.qmqm.pl</email>
</author>
<published>2020-05-04T22:37:57Z</published>
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<id>urn:sha1:03a1ee1dad0e39390ca397fff0cf84a3b1de1beb</id>
<content type='text'>
We need to have clocks accessible via phandle to select them
as peripheral clock parent using assigned-clock-parents in DT.
Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available.

Signed-off-by: Michał Mirosław &lt;mirq-linux@rere.qmqm.pl&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.pl
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: at91: allow setting PCKx parent via DT</title>
<updated>2020-05-27T03:22:43Z</updated>
<author>
<name>Michał Mirosław</name>
<email>mirq-linux@rere.qmqm.pl</email>
</author>
<published>2020-05-04T22:37:56Z</published>
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<id>urn:sha1:99767cd4406fd620d33fa7f820f50764453dc897</id>
<content type='text'>
This exposes PROGx clocks for use in assigned-clocks DeviceTree property
for selecting PCKx parent clock.

Signed-off-by: Michał Mirosław &lt;mirq-linux@rere.qmqm.pl&gt;
Link: https://lkml.kernel.org/r/0054532c00163ddf405dad658b32f0d7d97fcc8e.1588630999.git.mirq-linux@rere.qmqm.pl
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 4</title>
<updated>2019-05-21T09:28:40Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-19T13:51:34Z</published>
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<id>urn:sha1:a636cd6c422865a74ff305039ff0f85adbe3a7bf</id>
<content type='text'>
Based on 1 normalized pattern(s):

  licensed under gplv2 or later

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 118 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Jilayne Lovejoy &lt;opensource@jilayne.com&gt;
Reviewed-by: Steve Winslow &lt;swinslow@gmail.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.961286471@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
