<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/ast2600-clock.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
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<updated>2025-07-11T01:13:48Z</updated>
<entry>
<title>dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2</title>
<updated>2025-07-11T01:13:48Z</updated>
<author>
<name>Jacky Chou</name>
<email>jacky_chou@aspeedtech.com</email>
</author>
<published>2025-07-09T07:08:07Z</published>
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<id>urn:sha1:4dc5f7b2c0ccf233d16c5f3090208d70954f1e2a</id>
<content type='text'>
Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to
the ast2600-clock binding header. These are required for proper
reset control of the MAC1 and MAC2 ethernet controllers on the
AST2600 SoC.

Signed-off-by: Jacky Chou &lt;jacky_chou@aspeedtech.com&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Link: https://patch.msgid.link/20250709070809.2560688-3-jacky_chou@aspeedtech.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: ast2600: Add FSI clock</title>
<updated>2024-02-22T05:45:45Z</updated>
<author>
<name>Eddie James</name>
<email>eajames@linux.ibm.com</email>
</author>
<published>2024-02-15T22:07:27Z</published>
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<id>urn:sha1:692678b69cd61485ad831539b9f0bdf562406729</id>
<content type='text'>
Add a definition for the FSI clock.

Signed-off-by: Eddie James &lt;eajames@linux.ibm.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20240215220759.976998-2-eajames@linux.ibm.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: ast2600: Add I3C and MAC reset definitions</title>
<updated>2023-07-19T19:49:39Z</updated>
<author>
<name>Dylan Hung</name>
<email>kobedylan@gmail.com</email>
</author>
<published>2023-07-18T06:26:16Z</published>
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<id>urn:sha1:bbb8eb3cb06f66866726ddacfbf7c1411a40565d</id>
<content type='text'>
Add reset definitions of AST2600 I3C and MAC controllers. In the case of
the I3C reset, since there is no reset-line hardware available for
`ASPEED_RESET_I3C_DMA`, a new macro `ASPEED_RESET_I3C` with the same ID
is introduced to provide a more accurate representation of the hardware.
The old macro `ASPEED_RESET_I3C_DMA` is kept to provide backward
compatibility.

Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
Link: https://lore.kernel.org/r/20230718062616.2822339-1-dylan_hung@aspeedtech.com
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: ast2600: Expand comment on reset definitions</title>
<updated>2023-03-06T22:11:35Z</updated>
<author>
<name>Jeremy Kerr</name>
<email>jk@codeconstruct.com.au</email>
</author>
<published>2023-03-02T00:58:34Z</published>
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<id>urn:sha1:ced8a02b3452291171e9988a3c862c56e1628a1d</id>
<content type='text'>
The current "not part of a gate" is a little ambiguous. Expand this a
little to clarify the reference to the paired clock + reset control.

Signed-off-by: Jeremy Kerr &lt;jk@codeconstruct.com.au&gt;
Link: https://lore.kernel.org/r/20230302005834.13171-7-jk@codeconstruct.com.au
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Tested-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: ast2600: remove IC36 &amp; I3C7 clock definitions</title>
<updated>2023-03-06T22:11:25Z</updated>
<author>
<name>Jeremy Kerr</name>
<email>jk@codeconstruct.com.au</email>
</author>
<published>2023-03-02T00:58:32Z</published>
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<id>urn:sha1:1f15e0486b6e29d7b327d3150215ddec31fca679</id>
<content type='text'>
The current ast2600 clock definitions include entries for i3c6 and i3c7
devices, which don't exist: there are no clock control lines documented
for these, and only i3c devices 0 through 5 are present.

So, remove the definitions for I3C6 and I3C7. Although this is a
potential ABI-breaking change, there are no in-tree users of these, and
any references would be broken anyway, as the hardware doesn't exist.

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7
from Aspeed's own tree, originally by Dylan Hung
&lt;dylan_hung@aspeedtech.com&gt;.

Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Jeremy Kerr &lt;jk@codeconstruct.com.au&gt;
Link: https://lore.kernel.org/r/20230302005834.13171-5-jk@codeconstruct.com.au
Tested-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: ast2600: Add top-level I3C clock</title>
<updated>2023-03-06T22:11:09Z</updated>
<author>
<name>Jeremy Kerr</name>
<email>jk@codeconstruct.com.au</email>
</author>
<published>2023-03-02T00:58:30Z</published>
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<id>urn:sha1:1038b6978b438d954e2e827d4d553bed94cd83e0</id>
<content type='text'>
The ast2600 hardware has a top-level clock for all i3c controller
peripherals (then gated to each individual controller), so add a
top-level i3c clock line to control this.

This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7
from Aspeed's own tree, originally by Dylan Hung
&lt;dylan_hung@aspeedtech.com&gt;.

Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Jeremy Kerr &lt;jk@codeconstruct.com.au&gt;
Link: https://lore.kernel.org/r/20230302005834.13171-3-jk@codeconstruct.com.au
Tested-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: Add AST2500/AST2600 HACE reset definition</title>
<updated>2022-08-26T10:50:38Z</updated>
<author>
<name>Neal Liu</name>
<email>neal_liu@aspeedtech.com</email>
</author>
<published>2022-08-18T03:59:53Z</published>
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<id>urn:sha1:dffc3c566be3da314fdc98432dd166abb35aee03</id>
<content type='text'>
Add HACE reset bit definition for AST2500/AST2600.

Signed-off-by: Neal Liu &lt;neal_liu@aspeedtech.com&gt;
Signed-off-by: Johnny Huang &lt;johnny_huang@aspeedtech.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: Add AST2600 RMII RCLK gate definitions</title>
<updated>2019-11-01T04:31:18Z</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2019-10-10T02:07:24Z</published>
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<id>urn:sha1:d8d9ad83a497f78edd4016df0919a49628dcafbc</id>
<content type='text'>
The AST2600 has an explicit gate for the RMII RCLK for each of the four
MACs.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
</content>
</entry>
<entry>
<title>clk: Add support for AST2600 SoC</title>
<updated>2019-09-06T22:22:29Z</updated>
<author>
<name>Joel Stanley</name>
<email>joel@jms.id.au</email>
</author>
<published>2019-08-25T14:18:48Z</published>
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<id>urn:sha1:d3d04f6c330a60ce7170a1076b06f31c77ba7873</id>
<content type='text'>
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.

Signed-off-by: Joel Stanley &lt;joel@jms.id.au&gt;
Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au
[sboyd@kernel.org: Mark arrays const]
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
</feed>
