<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/drm/i915_pciids.h, branch linux-5.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-04-01T16:15:22Z</updated>
<entry>
<title>drm/i915: Split some PCI ids into separate groups</title>
<updated>2019-04-01T16:15:22Z</updated>
<author>
<name>Tvrtko Ursulin</name>
<email>tvrtko.ursulin@intel.com</email>
</author>
<published>2019-03-26T07:40:56Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4ae61358cc1ad537973b242cf390163a2f7b15b2'/>
<id>urn:sha1:4ae61358cc1ad537973b242cf390163a2f7b15b2</id>
<content type='text'>
This will enable the following patch to consolidate most device ids into
i915_pciids.h.

While cross-referencing the ids listed in i915_drv.h, with the ones listed
in i915_pciids.h, and also the comments in the latter, a bug for bug
approach was used. This means two things:

1.
Some ids are only present in i915_drv.h - obviously this means those parts
would not have been probed at all so they were not added to i915_pciids.h

2.
Some part type comments in i915_pciids.h were in disagreement with
i915_drv.h. For instance parts labeled as ULT or ULX were not considered
as such in i915_drv.h. The existing behaviour takes precedence here.

Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Suggested-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Cc: Jani Nikula &lt;jani.nikula@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190326074057.27833-4-tvrtko.ursulin@linux.intel.com
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
</content>
</entry>
<entry>
<title>drm/i915: Split Pineview device info into desktop and mobile</title>
<updated>2019-04-01T16:15:14Z</updated>
<author>
<name>Tvrtko Ursulin</name>
<email>tvrtko.ursulin@intel.com</email>
</author>
<published>2019-03-26T07:40:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=86d35d4e7625f7c056d81316da107bd3a7564fb3'/>
<id>urn:sha1:86d35d4e7625f7c056d81316da107bd3a7564fb3</id>
<content type='text'>
This allows the IS_PINEVIEW_&lt;G|M&gt; macros to be removed and avoid
duplication of device ids already defined in i915_pciids.h.

!IS_MOBILE check can be used in place of existing IS_PINEVIEW_G call
sites.

Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Suggested-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Cc: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190326074057.27833-2-tvrtko.ursulin@linux.intel.com
</content>
</entry>
<entry>
<title>drm/i915/ehl: Add EHL platform info and PCI IDs</title>
<updated>2019-03-22T19:51:08Z</updated>
<author>
<name>James Ausmus</name>
<email>james.ausmus@intel.com</email>
</author>
<published>2019-03-22T17:58:42Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=29f3863d33d1e2ad6c87fe64a61538041bd965bd'/>
<id>urn:sha1:29f3863d33d1e2ad6c87fe64a61538041bd965bd</id>
<content type='text'>
Add known EHL PCI IDs.

v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
   	      patch cc'ing the appropriated list and maintainers for
	      proper ack.
v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since GEN&amp;_FEATURES.
    	       - Added ppgtt type and size after rework from Bob and Chris
v4: (Rodrigo): - remove ppgtt type added on v3. Jose pointed it is not
    	       	 needed.

Cc: Bob Paauwe &lt;bob.j.paauwe@intel.com&gt;
Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: James Ausmus &lt;james.ausmus@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Bob Paauwe &lt;bob.j.paauwe@intel.com&gt;
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190322175847.25707-1-rodrigo.vivi@intel.com
</content>
</entry>
<entry>
<title>drm/i915/cml: Add CML PCI IDS</title>
<updated>2019-03-19T23:55:01Z</updated>
<author>
<name>Anusha Srivatsa</name>
<email>anusha.srivatsa@intel.com</email>
</author>
<published>2019-03-18T20:01:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a7b4deeb02b978bc59808cb13c93ba84f01023a4'/>
<id>urn:sha1:a7b4deeb02b978bc59808cb13c93ba84f01023a4</id>
<content type='text'>
Comet Lake is a Intel Processor containing Gen9
Intel HD Graphics. This patch adds the initial set of
PCI IDs. Comet Lake comes off of Coffee Lake - adding
the IDs to Coffee Lake ID list.

More support and features will be in the patches that follow.

v2: Split IDs according to GT. (Rodrigo)

v3: Update IDs.

Cc: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Cc: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Signed-off-by: Anusha Srivatsa &lt;anusha.srivatsa@intel.com&gt;
Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190318200133.9666-1-anusha.srivatsa@intel.com
</content>
</entry>
<entry>
<title>drm/i915: Add new ICL PCI ID</title>
<updated>2019-03-12T17:47:58Z</updated>
<author>
<name>José Roberto de Souza</name>
<email>jose.souza@intel.com</email>
</author>
<published>2019-03-08T21:56:46Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9a751b999d17a037d5562318d3a21dd5e5bd55eb'/>
<id>urn:sha1:9a751b999d17a037d5562318d3a21dd5e5bd55eb</id>
<content type='text'>
A new PCI ID for ICL was added to BSpec, lets keep it in tight sync
as ICL is not protected by the alpha support flag anymore.

v2: Keeping BSpec order(Rodrigo)

BSepc: 21141
Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190308215646.30436-1-jose.souza@intel.com
</content>
</entry>
<entry>
<title>drm/i915/cfl: Adding another PCI Device ID.</title>
<updated>2019-01-31T16:53:59Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2019-02-01T23:50:49Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5e0f5a58b167fc2c8352d90c0faa8c0c9ca75c26'/>
<id>urn:sha1:5e0f5a58b167fc2c8352d90c0faa8c0c9ca75c26</id>
<content type='text'>
While cross checking PCI IDs from Intel Media SDK
and kernel Dmitry noticed this gap. So we checked the
spec and this new ID had been recently added.

v2: Adding new H_GT1 entry to i915_pci.c (Jose)

Reported-by: Dmitry Rogozhkin&lt;dmitry.v.rogozhkin@intel.com&gt;
Cc: Dmitry Rogozhkin&lt;dmitry.v.rogozhkin@intel.com&gt;
Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190201235049.27206-1-rodrigo.vivi@intel.com
</content>
</entry>
<entry>
<title>drm/i915/icl: Adding few more device IDs for Ice Lake</title>
<updated>2019-01-23T11:57:14Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2019-01-18T05:59:43Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=03ca3cf8e9aa7549e6c398462af0f68bdd43e7fe'/>
<id>urn:sha1:03ca3cf8e9aa7549e6c398462af0f68bdd43e7fe</id>
<content type='text'>
We just got aware that there was more IDs available
at spec, so let's add them already.

Cc: James Ausmus &lt;james.ausmus@intel.com&gt;
Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Mika Kuoppala &lt;mika.kuoppala@linux.intel.com&gt;
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Mika Kuoppala &lt;mika.kuoppala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20190118055943.10252-1-rodrigo.vivi@intel.com
</content>
</entry>
<entry>
<title>drm/i915/aml: Add new Amber Lake PCI ID</title>
<updated>2018-10-11T17:59:34Z</updated>
<author>
<name>José Roberto de Souza</name>
<email>jose.souza@intel.com</email>
</author>
<published>2018-09-27T01:06:50Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c0c46ca461f136a0ae1ed69da6c874e850aeeb53'/>
<id>urn:sha1:c0c46ca461f136a0ae1ed69da6c874e850aeeb53</id>
<content type='text'>
This new AML PCI ID uses the same gen graphics as Coffe Lake not a
Kaby Lake one like the other AMLs.

So to make it more explicit renaming INTEL_AML_GT2_IDS to
INTEL_AML_KBL_GT2_IDS and naming this id as INTEL_AML_CFL_GT2_IDS.

v2:
- missed add new AML macro to INTEL_CFL_IDS()
- added derivated platform initials to AML macros

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20180927010650.22731-1-jose.souza@intel.com
</content>
</entry>
<entry>
<title>drm/i915: Redefine some Whiskey Lake SKUs</title>
<updated>2018-10-05T20:49:23Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2018-09-24T23:43:12Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c1c8f6fa731bc850d571d9c32016c3bf9ed1332e'/>
<id>urn:sha1:c1c8f6fa731bc850d571d9c32016c3bf9ed1332e</id>
<content type='text'>
commit 'b9be78531d27 ("drm/i915/whl: Introducing
Whiskey Lake platform")' introduced WHL by moving some
of CFL IDs here and using the Spec information of "U43" for
most of IDs what appeared to be GT3.

However when propagating the change to Mesa, Lionel noticed
that based on number of execution unities the classification
here seems at least strange.

So, let's move for now with the information we trust more:
the number of EUs. So we are able to propagate this change
across the stack without getting stuck forever.

Reference: https://patchwork.freedesktop.org/patch/246695/
Fixes: b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
Cc: Lionel Landwerlin &lt;lionel.g.landwerlin@intel.com&gt;
Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Cc: David Airlie &lt;airlied@linux.ie&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20180924234312.15017-1-rodrigo.vivi@intel.com
</content>
</entry>
<entry>
<title>drm/i915/cfl: Add a new CFL PCI ID.</title>
<updated>2018-08-09T05:31:05Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2018-08-03T23:27:21Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d0e062ebb3a44b56a7e672da568334c76f763552'/>
<id>urn:sha1:d0e062ebb3a44b56a7e672da568334c76f763552</id>
<content type='text'>
One more CFL ID added to spec.

Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20180803232721.20038-1-rodrigo.vivi@intel.com
</content>
</entry>
</feed>
