<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/drm/i915_pciids.h, branch linux-3.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-3.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-3.17.y'/>
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<updated>2014-06-24T11:56:16Z</updated>
<entry>
<title>drm/i915: BDW: Adding Reserved PCI IDs.</title>
<updated>2014-06-24T11:56:16Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2014-06-10T17:09:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fb7023e0e248a33cb00d0a9cdce0bcedaa1ad284'/>
<id>urn:sha1:fb7023e0e248a33cb00d0a9cdce0bcedaa1ad284</id>
<content type='text'>
These PCI IDs are reserved on BSpec and can be used at any time in the future.
So let's add this now in order to avoid issues that we already faced on previous
platforms, like finding out about new ids when user reported accelaration weren't
enabled.

Cc: stable@vger.kernel.org
Reviewed-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-next</title>
<updated>2014-06-05T10:28:59Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2014-06-05T10:28:59Z</published>
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<id>urn:sha1:8d4ad9d4bb0a618c975a32d77087694ec6336f68</id>
<content type='text'>
Merge drm-fixes into drm-next.

Both i915 and radeon need this done for later patches.

Conflicts:
	drivers/gpu/drm/drm_crtc_helper.c
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/i915/i915_gem.c
	drivers/gpu/drm/i915/i915_gem_execbuffer.c
	drivers/gpu/drm/i915/i915_gem_gtt.c
</content>
</entry>
<entry>
<title>srm/i915/chv: Add Cherryview PCI IDs</title>
<updated>2014-05-12T17:50:07Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2014-04-09T15:19:04Z</published>
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<id>urn:sha1:7d87a7f709650bde4d7d63117f25ee1c095da5dd</id>
<content type='text'>
v2: Update to also fill in the new num_pipes field.

v3: Rebase on top of the pciid extraction.

v4: Switch from info-&gt;has*ring to info-&gt;ring mask. Also add VEBOX support whiel
at it.

v5: s/CHV_PCI_IDS/CHV_IDS/, and drop the trailing '\'

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Reviewed-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Split the BDW device definition to prepare for dual BSD rings on BDW GT3</title>
<updated>2014-05-05T07:08:44Z</updated>
<author>
<name>Zhao Yakui</name>
<email>yakui.zhao@intel.com</email>
</author>
<published>2014-04-17T02:37:35Z</published>
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<id>urn:sha1:fd3c269f8ff940cc0fbb3b7f7e84c0572f6f759a</id>
<content type='text'>
Based on the hardware spec, the BDW GT3 has the different configuration
with the BDW GT1/GT2. So split the BDW device info definition.
This is to do the preparation for adding the Dual BSD rings on BDW GT3 machine.

V1-&gt;V2: Follow Daniel's comment to pay attention to the stolen check for BDW
in kernel/early-quirks.c

Reviewed-by: Imre Deak &lt;imre.deak@intel.com&gt;
Signed-off-by: Zhao Yakui &lt;yakui.zhao@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX</title>
<updated>2014-04-30T06:46:51Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2014-04-29T14:00:22Z</published>
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<id>urn:sha1:9bbfd20abe5025adbb0ac75160bd2e41158a9e83</id>
<content type='text'>
Because the docs say ULX doesn't support it on HSW.

Reviewed-by: Dave Airlie &lt;airlied@redhat.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/bdw: Add device IDs</title>
<updated>2013-11-08T17:09:36Z</updated>
<author>
<name>Ben Widawsky</name>
<email>benjamin.widawsky@intel.com</email>
</author>
<published>2013-11-04T00:47:33Z</published>
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<id>urn:sha1:4d4dead67a4ab1d5de393f15ed5e4e2aa63d3bcf</id>
<content type='text'>
v2: Squash in "drm/i915/bdw: Add BDW to the HAS_DDI check" as
suggested by Damien.

v3: Squash in VEBOX enabling from  Zhao Yakui &lt;yakui.zhao@intel.com&gt;

v4: Rebase on top of Jesse's patch to extract all pci ids to
include/drm/i915_pciids.h.

v4: Replace Halo by its marketing moniker Iris. Requested by Ben.

v5: Switch from info-&gt;has*ring to info-&gt;ring_mask.

v6: Add 0x16X2 variant (which is newer than this patch)
Rename to use new naming scheme (Chris)
Remove Simulator PCI ids. These snuck in during rebase (Chris)

v7: Fix poor sed job from v6
Make the desktop variants use the desktop macro (Rebase error). Notice
that this makes no functional difference - it's just confusing.

Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Reviewed-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: split PCI IDs out into i915_drm.h v4</title>
<updated>2013-09-03T17:17:56Z</updated>
<author>
<name>Jesse Barnes</name>
<email>jbarnes@virtuousgeek.org</email>
</author>
<published>2013-07-26T20:32:51Z</published>
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<id>urn:sha1:a0a1807544fe59b42d3760ee912ea4c6741298f5</id>
<content type='text'>
For use by userspace (at some point in the future) and other kernel code.

v2: move PCI IDs to uabi (Chris)
    move PCI IDs to drm/ (Dave)
v3: fixup Quanta detection - needs to come first (Daniel)
v4: fix up PCI match structure init for easier use by userspace (Chris)

Signed-off-by: Jesse Barnes &lt;jbarnes@virtuousgeek.org&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
</feed>
