kernel/include/asm-sparc64/tsb.h, branch linux-2.6.21.y

[PATCH] SPARC64: Fix two bugs wrt. kernel 4MB TSB.

2007-06-11T18:36:53Z

1) The TSB lookup was not using the correct hash mask. 2) It was not aligned on a boundary equal to it's size, which is required by the sun4v Hypervisor. wasn't having it's return value checked, and that bug will be fixed up as well in a subsequent changeset. Signed-off-by: David S. Miller Signed-off-by: Chris Wright Signed-off-by: Greg Kroah-Hartman

[SPARC64]: Get DEBUG_PAGEALLOC working again.

2007-03-17T00:20:28Z

We have to make sure to use base-pagesize TLB entries even during the early transition period where we need TLB miss handling but don't have the kernel page tables setup yet for the linear region. Also, it is necessary therefore to not use the 4MB TSB for these translations, and instead use the normal kernel TSB. This allows us to also get rid of the 4MB tsb for debug builds which shrinks the kernel a little bit. Signed-off-by: David S. Miller

[SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.

2006-03-20T09:13:56Z

It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller

[SPARC64]: More TLB/TSB handling fixes.

2006-03-20T09:13:34Z

The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller

[SPARC64]: Initial sun4v TLB miss handling infrastructure.

2006-03-20T09:11:52Z

Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller

[SPARC64]: Access TSB with physical addresses when possible.

2006-03-20T09:11:32Z

This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller

[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h

2006-03-20T09:11:31Z

Signed-off-by: David S. Miller

[SPARC64]: Increase swapper_tsb size to 32K.

2006-03-20T09:11:26Z

Signed-off-by: David S. Miller

[SPARC64]: Fix incorrect TSB lock bit handling.

2006-03-20T09:11:21Z

The TSB_LOCK_BIT define is actually a special value shifted down by 32-bits for the assembler code macros. In C code, this isn't what we want. Signed-off-by: David S. Miller

[SPARC64]: Add infrastructure for dynamic TSB sizing.

2006-03-20T09:11:17Z

This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller