<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/asm-i386/processor.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2007-10-11T09:20:03Z</updated>
<entry>
<title>i386/x86_64: move headers to include/asm-x86</title>
<updated>2007-10-11T09:20:03Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2007-10-11T09:20:03Z</published>
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<id>urn:sha1:96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42</id>
<content type='text'>
Move the headers to include/asm-x86 and fixup the
header install make rules

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86: Replace NSC/Cyrix specific chipset access macros by inlined functions.</title>
<updated>2007-07-22T18:03:38Z</updated>
<author>
<name>Juergen Beisert</name>
<email>juergen@kreuzholzen.de</email>
</author>
<published>2007-07-22T09:12:38Z</published>
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<id>urn:sha1:f25f64ed5bd3c2932493681bdfdb483ea707da0a</id>
<content type='text'>
Due to index register access ordering problems, when using macros a line
like this fails (and does nothing):

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);

With inlined functions this line will work as expected.

Note about a side effect: Seems on Geode GX1 based systems the
"suspend on halt power saving feature" was never enabled due to this
wrong macro expansion. With inlined functions it will be enabled, but
this will stop the TSC when the CPU runs into a HLT instruction.
Kernel output something like this:
	Clocksource tsc unstable (delta = -472746897 ns)

This is the 3rd version of this patch.

 - Adding missed arch/i386/kernel/cpu/mtrr/state.c
	Thanks to Andres Salomon
 - Adding some big fat comments into the new header file
 	Suggested by Andi Kleen

AK: fixed x86-64 compilation

Signed-off-by: Juergen Beisert &lt;juergen@kreuzholzen.de&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>x86: remove support for the Rise CPU</title>
<updated>2007-07-22T01:37:10Z</updated>
<author>
<name>Adrian Bunk</name>
<email>bunk@stusta.de</email>
</author>
<published>2007-07-21T15:10:46Z</published>
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<id>urn:sha1:9596017e79cddb4f4fd4b896425a30f86946ce85</id>
<content type='text'>
The Rise CPUs were only very short-lived, and there are no reports of
anyone both owning one and running Linux on it.

Googling for the printk string "CPU: Rise iDragon" didn't find any dmesg
available online.

If it turns out that against all expectations there are actually users
reverting this patch would be easy.

This patch will make the kernel images smaller by a few bytes for all
i386 users.

Signed-off-by: Adrian Bunk &lt;bunk@stusta.de&gt;
Acked-by: Dave Jones &lt;davej@redhat.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>make seccomp zerocost in schedule</title>
<updated>2007-07-16T16:05:50Z</updated>
<author>
<name>Andrea Arcangeli</name>
<email>andrea@cpushare.com</email>
</author>
<published>2007-07-16T06:41:33Z</published>
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<id>urn:sha1:cf99abace7e07dd8491e7093a9a9ef11d48838ed</id>
<content type='text'>
This follows a suggestion from Chuck Ebbert on how to make seccomp
absolutely zerocost in schedule too.  The only remaining footprint of
seccomp is in terms of the bzImage size that becomes a few bytes (perhaps
even a few kbytes) larger, measure it if you care in the embedded.

Signed-off-by: Andrea Arcangeli &lt;andrea@cpushare.com&gt;
Cc: Andi Kleen &lt;ak@suse.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>Use a new CPU feature word to cover features that are spread around</title>
<updated>2007-07-12T17:55:54Z</updated>
<author>
<name>Venki Pallipadi</name>
<email>venkatesh.pallipadi@intel.com</email>
</author>
<published>2007-07-11T19:18:32Z</published>
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<id>urn:sha1:1d67953f2bda8876045c24ae58841f27d9bb7572</id>
<content type='text'>
Some Intel features are spread around in different CPUID leafs like 0x5,
0x6 and 0xA.  Make this feature detection code common across i386 and
x86_64.

Display Intel Dynamic Acceleration feature in /proc/cpuinfo. This feature
will be enabled automatically by current acpi-cpufreq driver.

Refer to Intel Software Developer's Manual for more details about the feature.

Thanks to hpa (H Peter Anvin) for the making the actual code detecting the
scattered features data-driven.

Signed-off-by: Venkatesh Pallipadi &lt;venkatesh.pallipadi@intel.com&gt;
Signed-off-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>i386: move common parts of smp into their own file</title>
<updated>2007-05-15T15:54:00Z</updated>
<author>
<name>Jeremy Fitzhardinge</name>
<email>jeremy@goop.org</email>
</author>
<published>2007-05-15T08:41:48Z</published>
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<id>urn:sha1:297d9c035edd04327fedc0d1da27c2b112b66fcc</id>
<content type='text'>
Several parts of kernel/smp.c and smpboot.c are generally useful for other
subarchitectures and paravirt_ops implementations, so make them available for
reuse.

Signed-off-by: Jeremy Fitzhardinge &lt;jeremy@xensource.com&gt;
Acked-by: Chris Wright &lt;chrisw@sous-sol.org&gt;
Cc: James Bottomley &lt;James.Bottomley@HansenPartnership.com&gt;
Cc: Eric W. Biederman &lt;ebiederm@xmission.com&gt;
Cc: Andi Kleen &lt;ak@suse.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>[PATCH] i386: Fix UP gdt bugs</title>
<updated>2007-05-02T17:27:16Z</updated>
<author>
<name>Jeremy Fitzhardinge</name>
<email>jeremy@goop.org</email>
</author>
<published>2007-05-02T17:27:16Z</published>
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<id>urn:sha1:c5413fbe894924ddb8aa474a4d4da52e7a6c7e0b</id>
<content type='text'>
Fixes two problems with the GDT when compiling for uniprocessor:
 - There's no percpu segment, so trying to load its selector into %fs fails.
   Use a null selector instead.
 - The real gdt needs to be loaded at some point.  Do it in cpu_init().

Signed-off-by: Chris Wright &lt;chrisw@sous-sol.org&gt;
Signed-off-by: Jeremy Fitzhardinge &lt;jeremy@xensource.com&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
Cc: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
</content>
</entry>
<entry>
<title>[PATCH] i386: Convert PDA into the percpu section</title>
<updated>2007-05-02T17:27:16Z</updated>
<author>
<name>Jeremy Fitzhardinge</name>
<email>jeremy@goop.org</email>
</author>
<published>2007-05-02T17:27:16Z</published>
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<id>urn:sha1:7c3576d261ce046789a7db14f43303f8120910c7</id>
<content type='text'>
Currently x86 (similar to x84-64) has a special per-cpu structure
called "i386_pda" which can be easily and efficiently referenced via
the %fs register.  An ELF section is more flexible than a structure,
allowing any piece of code to use this area.  Indeed, such a section
already exists: the per-cpu area.

So this patch:
(1) Removes the PDA and uses per-cpu variables for each current member.
(2) Replaces the __KERNEL_PDA segment with __KERNEL_PERCPU.
(3) Creates a per-cpu mirror of __per_cpu_offset called this_cpu_off, which
    can be used to calculate addresses for this CPU's variables.
(4) Simplifies startup, because %fs doesn't need to be loaded with a
    special segment at early boot; it can be deferred until the first
    percpu area is allocated (or never for UP).

The result is less code and one less x86-specific concept.

Signed-off-by: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
Signed-off-by: Jeremy Fitzhardinge &lt;jeremy@xensource.com&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
Cc: Andi Kleen &lt;ak@suse.de&gt;
</content>
</entry>
<entry>
<title>[PATCH] i386: i386 separate hardware-defined TSS from Linux additions</title>
<updated>2007-05-02T17:27:13Z</updated>
<author>
<name>Rusty Russell</name>
<email>rusty@rustcorp.com.au</email>
</author>
<published>2007-05-02T17:27:13Z</published>
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<id>urn:sha1:a75c54f933bd8db9f4a609bd128663c179b3e6a1</id>
<content type='text'>
On Thu, 2007-03-29 at 13:16 +0200, Andi Kleen wrote:
&gt; Please clean it up properly with two structs.

Not sure about this, now I've done it.  Running it here.

If you like it, I can do x86-64 as well.

==
lguest defines its own TSS struct because the "struct tss_struct"
contains linux-specific additions.  Andi asked me to split the struct
in processor.h.

Unfortunately it makes usage a little awkward.

Signed-off-by: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
</content>
</entry>
<entry>
<title>[PATCH] x86: Clean up x86 control register and MSR macros (corrected)</title>
<updated>2007-05-02T17:27:12Z</updated>
<author>
<name>H. Peter Anvin</name>
<email>hpa@zytor.com</email>
</author>
<published>2007-05-02T17:27:12Z</published>
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<id>urn:sha1:4bc5aa91fb1e544ad37805520030a0d9fc6e11d3</id>
<content type='text'>
This patch is based on Rusty's recent cleanup of the EFLAGS-related
macros; it extends the same kind of cleanup to control registers and
MSRs.

It also unifies these between i386 and x86-64; at least with regards
to MSRs, the two had definitely gotten out of sync.

Signed-off-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
</content>
</entry>
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