<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/acpi/actbl2.h, branch linux-5.11.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2020-03-30T12:52:33Z</updated>
<entry>
<title>ACPICA: Add NHLT table signature</title>
<updated>2020-03-30T12:52:33Z</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2020-03-27T22:21:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=88055d8f4a715d52b9b981f717e9e51cf4668d5d'/>
<id>urn:sha1:88055d8f4a715d52b9b981f717e9e51cf4668d5d</id>
<content type='text'>
ACPICA commit 422166b656565d180bb3aac712009bdce5e70cdd

NHLT (Non-HDAudio Link Table) provides configuration of audio
endpoints for Intel SST (Smart Sound Technology) DSP products.
Similarly to other ACPI tables, data provided by BIOS may not
describe it correctly, thus overriding is required.

ACPI override mechanism checks for unknown signature before
proceeding. Update known signatures array to support NHLT.

Link: https://github.com/acpica/acpica/commit/422166b6
Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Erik Kaneda &lt;erik.kaneda@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: Fix IVRS IVHD type 10h reserved field name</title>
<updated>2020-03-30T12:52:32Z</updated>
<author>
<name>Michał Żygowski</name>
<email>michal.zygowski@3mdeb.com</email>
</author>
<published>2020-03-27T22:21:03Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=0dc7e795204c830812c79795fd17b329d9a8cbab'/>
<id>urn:sha1:0dc7e795204c830812c79795fd17b329d9a8cbab</id>
<content type='text'>
ACPICA commit 87a1ab2b2a63e28776261c48bdbae345f790d05d

According to AMD IOMMU Specification Revision 3.05 the reserved field
should be IOMMU Feature Reporting. Change the name of the field to the
correct one.

Link: https://github.com/acpica/acpica/commit/87a1ab2b
Signed-off-by: Michał Żygowski &lt;michal.zygowski@3mdeb.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Erik Kaneda &lt;erik.kaneda@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: Implement IVRS IVHD type 11h parsing</title>
<updated>2020-03-30T12:52:32Z</updated>
<author>
<name>Michał Żygowski</name>
<email>michal.zygowski@3mdeb.com</email>
</author>
<published>2020-03-27T22:21:02Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1f6239ca16fda8048367d47fc4979cbe8f8c658f'/>
<id>urn:sha1:1f6239ca16fda8048367d47fc4979cbe8f8c658f</id>
<content type='text'>
ACPICA commit 6ddc19419896e4149ced1b5f35f0dc12516c0399

The AMD IVRS table parsing supported only IVHD type 10h structures.
Parsing an IVHD type 11h caused the iasl to report unknown subtable type.
Add necessary structure definition for IVHD type 11h and apply correct
parsing method based on subtable type.

Link: https://github.com/acpica/acpica/commit/6ddc1941
Signed-off-by: Michał Żygowski &lt;michal.zygowski@3mdeb.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Erik Kaneda &lt;erik.kaneda@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: All acpica: Update copyrights to 2020 Including tool signons.</title>
<updated>2020-01-13T10:52:48Z</updated>
<author>
<name>Bob Moore</name>
<email>robert.moore@intel.com</email>
</author>
<published>2020-01-10T19:31:49Z</published>
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<id>urn:sha1:800ba7c5eaaa734e4bd66bf0441fc200bbcdca54</id>
<content type='text'>
ACPICA commit 8b9c69d0984067051ffbe8526f871448ead6a26b

Link: https://github.com/acpica/acpica/commit/8b9c69d0
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Erik Kaneda &lt;erik.kaneda@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPI/ACPICA: Trivial: fix spelling mistakes and fix whitespace formatting</title>
<updated>2019-02-24T20:12:01Z</updated>
<author>
<name>Erik Schmauss</name>
<email>erik.schmauss@intel.com</email>
</author>
<published>2019-02-15T21:36:19Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c163f90cc8620716b08ac7987c4c4ebf16444fd5'/>
<id>urn:sha1:c163f90cc8620716b08ac7987c4c4ebf16444fd5</id>
<content type='text'>
Signed-off-by: Erik Schmauss &lt;erik.schmauss@intel.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: ACPI 6.3: PPTT add additional fields in Processor Structure Flags</title>
<updated>2019-02-24T20:12:00Z</updated>
<author>
<name>Erik Schmauss</name>
<email>erik.schmauss@intel.com</email>
</author>
<published>2019-02-15T21:36:16Z</published>
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<id>urn:sha1:b5eab512e7cffb2bb37c4b342b5594e9e75fd486</id>
<content type='text'>
ACPICA commit c736ea34add19a3a07e0e398711847cd6b95affd

Link: https://github.com/acpica/acpica/commit/c736ea34
Signed-off-by: Erik Schmauss &lt;erik.schmauss@intel.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: ACPI 6.3: MADT: add support for statistical profiling in GICC</title>
<updated>2019-02-24T20:11:59Z</updated>
<author>
<name>Erik Schmauss</name>
<email>erik.schmauss@intel.com</email>
</author>
<published>2019-02-15T21:36:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e646e0a50cfadae315f2db05e07a2ec072ce8d9c'/>
<id>urn:sha1:e646e0a50cfadae315f2db05e07a2ec072ce8d9c</id>
<content type='text'>
ACPICA commit 31b184052a986dc8d80c878edeca574d4ffa1cf5

Link: https://github.com/acpica/acpica/commit/31b18405
Signed-off-by: Erik Schmauss &lt;erik.schmauss@intel.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: ACPI 6.3: Add Trigger order to PCC Identifier structure in PDTT</title>
<updated>2019-02-18T10:21:11Z</updated>
<author>
<name>Erik Schmauss</name>
<email>erik.schmauss@intel.com</email>
</author>
<published>2019-02-15T21:36:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f00175d06b50a9fe7ed076dd73a8d0c36a9ef22e'/>
<id>urn:sha1:f00175d06b50a9fe7ed076dd73a8d0c36a9ef22e</id>
<content type='text'>
ACPICA commit b11446d8b47805c2637a2286aca34b717ec6b5be

Link: https://github.com/acpica/acpica/commit/b11446d8
Signed-off-by: Erik Schmauss &lt;erik.schmauss@intel.com&gt;
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: All acpica: Update copyrights to 2019</title>
<updated>2019-01-15T17:04:02Z</updated>
<author>
<name>Bob Moore</name>
<email>robert.moore@intel.com</email>
</author>
<published>2019-01-14T17:55:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=840c02ca2215af648c781ae680d93d8aecd083b7'/>
<id>urn:sha1:840c02ca2215af648c781ae680d93d8aecd083b7</id>
<content type='text'>
ACPICA commit 62f4f98e941d86e41969bf2ab5a93b8dc94dc49e

The update includes userspace tool signons.

Link: https://github.com/acpica/acpica/commit/62f4f98e
Signed-off-by: Bob Moore &lt;robert.moore@intel.com&gt;
Signed-off-by: Erik Schmauss &lt;erik.schmauss@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPICA: IORT: Add PMCG node supprt</title>
<updated>2018-06-06T06:53:42Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2018-06-01T19:06:39Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a53eaef6da5dc0abd899d6512a31c6d94c92f9be'/>
<id>urn:sha1:a53eaef6da5dc0abd899d6512a31c6d94c92f9be</id>
<content type='text'>
PMCG nodes were added by IORT revision C, with the unfortunate oversight
that it only defined a single base address, and thus was incapable of
properly describing PMCG implementations with PMCG_CFGR.RELOC_CTRS = 1,
where the counters are in a separate page from the control registers.

Revision D corrects this by clarifying the existing field as the page 0
base address and adding a second field to describe the page 1 address
when implemented. With the spec now fit for purpose, let's support it.

Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Erik Schmauss &lt;erik.schmauss@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
</feed>
