kernel/drivers/usb/dwc3/dwc3-octeon.c, branch linux-6.9.y

Merge tag 'mips_6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2023-09-07T17:35:14Z

Pull MIPS updates from Thomas Bogendoerfer: "Just cleanups and fixes" * tag 'mips_6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: TXx9: Do PCI error checks on own line arch/mips/configs/*_defconfig cleanup MIPS: VDSO: Conditionally export __vdso_gettimeofday() Mips: loongson3_defconfig: Enable ast drm driver by default mips: remove mips: replace #include with #include mips: remove unneeded #include MIPS: Loongson64: Fix more __iomem attributes MIPS: loongson32: Remove regs-rtc.h MIPS: loongson32: Remove regs-clk.h MIPS: More explicit DT include clean-ups MIPS: Fixup explicit DT include clean-up Revert MIPS: Loongson: Fix build error when make modules_install MIPS: Only fiddle with CHECKFLAGS if `need-compiler' MIPS: Fix CONFIG_CPU_DADDI_WORKAROUNDS `modules_install' regression MIPS: Explicitly include correct DT includes

usb: dwc3: remove unnecessary platform_set_drvdata()

2023-08-22T12:45:19Z

Remove unnecessary platform_set_drvdata(..., NULL) in ->remove(), the driver_data will be cleared in device_unbind_cleanup() after calling ->remove() in driver call code. Signed-off-by: Yang Yingliang Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/20230810134710.114356-1-yangyingliang@huawei.com Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Verify clock divider

2023-08-09T12:15:52Z

Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into H_CLKDIV_SEL field. Signed-off-by: Ladislav Michl Reported-by: Linux Kernel Functional Testing Closes: https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZNIM7tlBNdHFzXZG@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Add SPDX header and copyright

2023-08-04T12:52:15Z

Assign copyright to indicate driver rewrite is done for RACOM s.r.o. As David no longer works for Marvell (Cavium), I'm to blame for breakage. Signed-off-by: Ladislav Michl Acked-by: Thinh Nguyen Acked-by: David Daney Reviewed-by: Philippe Mathieu-Daudé Link: https://lore.kernel.org/r/ZMeAAYx6Z3hlQBNQ@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Dump control register on clock init failure

2023-08-04T12:52:15Z

It might be interesting to know control register value in case clock fails to enable. Signed-off-by: Ladislav Michl Reviewed-by: Philippe Mathieu-Daudé Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZMd/5OX9szEMnhQH@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Move node parsing into driver probe

2023-08-04T12:52:15Z

Parse and verify device tree node first, then setup UCTL bridge using verified values. This avoids needless allocations in case DT misconfiguration was found in the middle of setup. Signed-off-by: Ladislav Michl Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZMd/x3MHA4/QowMO@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Avoid half-initialized controller state

2023-08-04T12:52:15Z

Power gpio configuration is done from the middle of dwc3_octeon_clocks_start leaving hardware in half-initialized state if it fails. As that indicates dwc3_octeon_clocks_start does more than just initialize the clocks rename it appropriately and verify power gpio configuration in advance at the beginning of device probe. Signed-off-by: Ladislav Michl Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZMd/oMRx8ze22/kK@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Pass dwc3_octeon to setup functions

2023-08-04T12:52:15Z

Pass dwc3_octeon instead of just the base. It fits with the function names and it requires less change in the future if access to dwc3_octeon is needed. Signed-off-by: Ladislav Michl Reviewed-by: Philippe Mathieu-Daudé Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZMd/gt58laSlqAAT@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Use _ULL bitfields defines

2023-08-04T12:52:15Z

While driver is intended to run on 64bit machines, it is compile time tested for 32bit targets as well. Here shift count overflow is reported for bits greater than 31, so use _ULL versions of BIT and GENMASK macros to silence these warnings. Signed-off-by: Ladislav Michl Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307260537.MROrhVNM-lkp@intel.com/ Reviewed-by: Philippe Mathieu-Daudé Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZMd/aa2ncz6tJGNU@lenoch Signed-off-by: Greg Kroah-Hartman

usb: dwc3: dwc3-octeon: Convert to glue driver

2023-08-04T12:52:15Z

DWC3 as implemented in Cavium SoC is using UCTL bridge unit between I/O interconnect and USB controller. Currently there is no bond with dwc3 core code, so if anything goes wrong in UCTL setup dwc3 is left in reset, which leads to bus error while trying to read any device register. Thus any failure in UCTL initialization ends with kernel panic. To avoid this move Octeon DWC3 glue code from arch/mips and make it proper glue driver which is used instead of dwc3-of-simple. Signed-off-by: Ladislav Michl Acked-by: Thomas Bogendoerfer Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/ZMd/ReyiY7wS6DvN@lenoch Signed-off-by: Greg Kroah-Hartman