kernel/drivers/spi/spi-sun6i.c, branch 0x221E-v0.0.1-v6.19

spi: sun6i: Support A523's SPI controllers

2025-12-22T09:00:50Z

The A523 has four SPI controllers. One of them supports MIPI DBI mode in addition to standard SPI. Compared to older generations, this newer controller now has a combined counter for the RX FIFO ad buffer levels. In older generations, the RX buffer level was a separate bitfield in the FIFO status register. In practice this difference is negligible. The buffer is mostly invisible to the implementation. If programmed I/O transfers are limited to the FIFO size, then the contents of the buffer seem to always be flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied to the FIFO levels. In all other aspects, the controller is the same as the one in the R329. Support the standard SPI mode controllers using the settings for R329. DBI is left out as there currently is no infrastructure for enabling a DBI host controller, as was the case for the R329. Also fold the entry for the R329 to make the style consistent. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20251221110513.1850535-3-wens@kernel.org Signed-off-by: Mark Brown

spi: Switch back to struct platform_driver::remove()

2024-09-29T23:12:23Z

After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/spi to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. The change for the spi-npcm-fiu stands out in the diffstat because the inconsistent formatting style of the platform_driver initializer is fixed to match the other struct initializer in the file. Signed-off-by: Uwe Kleine-König Link: https://patch.msgid.link/20240925113501.25208-2-u.kleine-koenig@baylibre.com Signed-off-by: Mark Brown

spi: sun6i: use 'time_left' variable with wait_for_completion_timeout()

2024-04-30T14:57:31Z

There is a confusing pattern in the kernel to use a variable named 'timeout' to store the result of wait_for_completion_timeout() causing patterns like: timeout = wait_for_completion_timeout(...) if (!timeout) return -ETIMEDOUT; with all kinds of permutations. Use 'time_left' as a variable to make the code self explaining. Fix to the proper variable type 'unsigned long' while here. Signed-off-by: Wolfram Sang Acked-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240430114142.28551-8-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown

spi: sun6i: switch to use modern name

2023-12-11T12:54:58Z

Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang Link: https://msgid.link/r/20231128093031.3707034-8-yangyingliang@huawei.com Signed-off-by: Mark Brown

Merge tag 'spi-fix-v6.6-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

2023-09-07T22:49:20Z

Pull spi fixes from Mark Brown: "A couple of fixes for the sun6i driver. The patch to reduce DMA RX to single byte width all the time is *hopefully* excessively cautious but it's unclear which SoCs are affected so the fix just covers everything for safety" * tag 'spi-fix-v6.6-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: sun6i: fix race between DMA RX transfer completion and RX FIFO drain spi: sun6i: reduce DMA RX transfer width to single byte

spi: sun6i: fix race between DMA RX transfer completion and RX FIFO drain

2023-09-04T12:55:29Z

Previously the transfer complete IRQ immediately drained to RX FIFO to read any data remaining in FIFO to the RX buffer. This behaviour is correct when dealing with SPI in interrupt mode. However in DMA mode the transfer complete interrupt still fires as soon as all bytes to be transferred have been stored in the FIFO. At that point data in the FIFO still needs to be picked up by the DMA engine. Thus the drain procedure and DMA engine end up racing to read from RX FIFO, corrupting any data read. Additionally the RX buffer pointer is never adjusted according to DMA progress in DMA mode, thus calling the RX FIFO drain procedure in DMA mode is a bug. Fix corruptions in DMA RX mode by draining RX FIFO only in interrupt mode. Also wait for completion of RX DMA when in DMA mode before returning to ensure all data has been copied to the supplied memory buffer. Signed-off-by: Tobias Schramm Link: https://lore.kernel.org/r/20230827152558.5368-3-t.schramm@manjaro.org Signed-off-by: Mark Brown

spi: sun6i: reduce DMA RX transfer width to single byte

2023-09-04T12:55:29Z

Through empirical testing it has been determined that sometimes RX SPI transfers with DMA enabled return corrupted data. This is down to single or even multiple bytes lost during DMA transfer from SPI peripheral to memory. It seems the RX FIFO within the SPI peripheral can become confused when performing bus read accesses wider than a single byte to it during an active SPI transfer. This patch reduces the width of individual DMA read accesses to the RX FIFO to a single byte to mitigate that issue. Signed-off-by: Tobias Schramm Link: https://lore.kernel.org/r/20230827152558.5368-2-t.schramm@manjaro.org Signed-off-by: Mark Brown

spi: Explicitly include correct DT includes

2023-07-14T19:53:00Z

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230714174955.4064174-1-robh@kernel.org Signed-off-by: Mark Brown

spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s

2023-07-09T21:51:27Z

Listed SoCs have SPI controllers that can operate in dual or quad modes. This patch adds dual/quad mode bits for spi_master on these SoCS. Signed-off-by: Maksim Kiselev Link: https://lore.kernel.org/r/20230624131632.2972546-3-bigunclemax@gmail.com Signed-off-by: Mark Brown

spi: sun6i: add quirk for dual and quad SPI modes support

2023-07-09T21:51:26Z

New Allwinner's SPI controllers can support dual and quad SPI modes. To enable one of these modes, we should set the corresponding bit in the SUN6I_BURST_CTL_CNT_REG register. DRM (28 bits) for dual mode and Quad_EN (29 bits) for quad transmission. Signed-off-by: Maksim Kiselev Link: https://lore.kernel.org/r/20230624131632.2972546-2-bigunclemax@gmail.com Signed-off-by: Mark Brown