<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/soc/imx, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
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<updated>2019-01-14T01:42:22Z</updated>
<entry>
<title>soc: imx: Break dependency on SOC_IMX8MQ for GPCv2</title>
<updated>2019-01-14T01:42:22Z</updated>
<author>
<name>Abel Vesa</name>
<email>abel.vesa@nxp.com</email>
</author>
<published>2019-01-12T08:56:31Z</published>
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<id>urn:sha1:9b0bb07328f2375b2b6d3f8343edb1ee1ed39307</id>
<content type='text'>
Since this is going to be used on more SoCs than just i.MX8MQ, make
the dependency here more generic by using ARCH_MXC instead.
Also remove the SOC_IMX7D since it is also included by the ARCH_MXC.

Signed-off-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Reviewed-by: Dong Aisheng &lt;aisheng.dong@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: handle reset clocks</title>
<updated>2019-01-11T07:12:59Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2018-12-17T15:31:52Z</published>
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<id>urn:sha1:ae1d2add26a4a0d34dc0615d304be2f341202e77</id>
<content type='text'>
Some power domains handled by the GPCv2 driver need to enable the clocks
for devies inside the domain, so that the reset propagation and proper
power-up sequencing happens. Handle them in the same way as on GPCv1.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: handle additional power-down bits in handshake register</title>
<updated>2019-01-11T07:12:38Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2018-12-17T15:31:51Z</published>
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<id>urn:sha1:b798d5a1b0eaf276f463262284e58a29b451063c</id>
<content type='text'>
Some of the i.MX8MQ domains have an additional control bit in the PU
handshake (HSK) register. Documentation about this bit is a bit sparse
at the moment, but it seems that it controls a power-down request to
the AMBA domain bridge (ADB-400) attached to those domains.

As the documentation doesn't desribe the usage of this bit yet, handle
it in the same way as done in the ATF implementation.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpc: Increase GPC_CLK_MAX to 7</title>
<updated>2018-12-10T00:51:12Z</updated>
<author>
<name>Leonard Crestez</name>
<email>leonard.crestez@nxp.com</email>
</author>
<published>2018-10-08T18:06:19Z</published>
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<id>urn:sha1:b6444cf5fa607469d9a14edef2edad32773f4514</id>
<content type='text'>
The DISPLAY power domain on imx6sx has 7 clocks.

Signed-off-by: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: add support for i.MX8MQ SoC</title>
<updated>2018-12-05T00:50:36Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2018-11-16T15:49:27Z</published>
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<id>urn:sha1:685efffe37c921cf1d56dd3c8617dc67bc343a99</id>
<content type='text'>
The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the
GPCv2 on the i.MX7, but only controls more power domains with a
different mapping.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: move register access table to domain data</title>
<updated>2018-12-05T00:50:34Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2018-11-16T15:49:26Z</published>
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<id>urn:sha1:e125dcba83f59b87b1db30f5b7075705d95cfcf7</id>
<content type='text'>
The valid register ranges are defined by the implemented power domains,
which are different between the individual SoCs where the GPCv2 is used.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: prefix i.MX7 specific defines</title>
<updated>2018-12-05T00:50:19Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2018-11-16T15:49:25Z</published>
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<id>urn:sha1:a800f418420d37f60fa471665a156c45d2702437</id>
<content type='text'>
So we can add i.MX8M support without introducing name clashes.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: Switch to SPDX identifier</title>
<updated>2018-10-01T05:24:15Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2018-09-18T17:48:14Z</published>
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<id>urn:sha1:8d8e3b7d8f06f69005d829d4a195b00ef976004b</id>
<content type='text'>
Adopt the SPDX license identifier headers to ease license compliance
management.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpc: Switch to SPDX identifier</title>
<updated>2018-10-01T05:24:15Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2018-09-18T17:48:13Z</published>
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<id>urn:sha1:2fe761d18adaf62686254fa273773efa6b1da9c0</id>
<content type='text'>
Adopt the SPDX license identifier headers to ease license compliance
management.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms</title>
<updated>2018-10-01T05:24:14Z</updated>
<author>
<name>Anson Huang</name>
<email>Anson.Huang@nxp.com</email>
</author>
<published>2018-08-28T08:36:46Z</published>
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<id>urn:sha1:73f59712a1a3e532a2cbfe582ecfdbf56c33297d</id>
<content type='text'>
i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they
can reuse gpcv2 pgc driver for power domain control, this
patch renames all functions and structure definitions started
with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to
pass platform specific power domain data for power domain
driver, thus make gpcv2 pgc driver more generic for i.MX
platforms.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Acked-by: Andrey Smirnov &lt;andrew.smirnov@gmail.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
</feed>
