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<title>kernel/drivers/sh/pfc.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2012-07-10T02:49:30Z</updated>
<entry>
<title>sh: pfc: Shuffle PFC support core.</title>
<updated>2012-07-10T02:49:30Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2012-07-10T02:49:30Z</published>
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<id>urn:sha1:afae021abeadc58aec5074f26a1d62912773edf7</id>
<content type='text'>
This follows the intc/clk changes and shuffles the PFC support code under
its own directory. This will facilitate better code sharing, and allow us
to trim down the exported interface by quite a margin.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Verify pin type encoding size at build time.</title>
<updated>2012-06-20T15:03:41Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2012-06-20T15:03:41Z</published>
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<id>urn:sha1:06d5631f56460917af3d9417ef63811cf0cad9ce</id>
<content type='text'>
The encoding is tightly packed, and future changes (such as
pinconf-generic support) can easily lead to a situation where we violate
the encoding constraints and trample data bit/reg bits. This plugs in
some sanity checks by way of a BUILD_BUG_ON() to blow up if we fail to
fit.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Split out gpio chip support.</title>
<updated>2012-06-20T08:29:04Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2012-06-20T08:29:04Z</published>
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<id>urn:sha1:b3c185a7614cd95ea9b68d89a8d1ee4227ee9018</id>
<content type='text'>
This implements a bit of rework for the PFC code, making the core itself
slightly more pluggable and moving out the gpio chip handling completely.

The API is preserved in such a way that platforms that depend on it for
early configuration are still able to do so, while making it possible to
migrate to alternate interfaces going forward.

This is the first step of chainsawing necessary to support the pinctrl
API, with the eventual goal being able to decouple pin function state
from the gpio API while retaining gpio chip tie-in for gpio pin functions
only, relying on the pinctrl/pinmux API for non-gpio function demux.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Unlock register support</title>
<updated>2012-01-09T00:33:57Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-12-13T16:01:14Z</published>
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<id>urn:sha1:e499ada829cf769ac6f16627cd9f09b855a7fd6d</id>
<content type='text'>
Add PFC support for a 32-bit unlock register. Needed to
drive the r8a7779 PFC that comes with a funky PMMR register.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Variable bitfield width config register support</title>
<updated>2012-01-09T00:33:55Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-12-13T16:01:05Z</published>
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<id>urn:sha1:f78a26f55b2438c439609fc90b473f7f08f5b697</id>
<content type='text'>
Add support for variable config reg hardware by adding
the macro PINMUX_CFG_REG_VAR(). The width of each bitfield
needs to be passed to the macro, and the correct space must
be consumed by each bitfield in the enum table following the
macro. Data registers still need to have fixed bitfields.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Add config_reg_helper() function</title>
<updated>2012-01-09T00:33:52Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-12-13T16:00:55Z</published>
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<id>urn:sha1:18925e118b3b4d55b45711218cd3c3c4360e5cd1</id>
<content type='text'>
Add a helper function for shared config reg access
calculations. This allows us to reduce the amount
of duplicated code, and at the same time prepare
for a common place for future variable bitwidth
config reg support.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Convert index to field and value pair</title>
<updated>2012-01-09T00:33:51Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-12-13T16:00:46Z</published>
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<id>urn:sha1:ad4a07ff8da7147b391f1ff0034f313a8b9da9e5</id>
<content type='text'>
Update the way the PFC code is passing bitfield
selection between configure register functions.

Convert the code from using index only to bitfield
number and selected value. First step towards future
variable bitfield width support.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Add gpio_read_bit() for data register access</title>
<updated>2012-01-09T00:33:50Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-12-13T16:00:37Z</published>
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<id>urn:sha1:92554d97c6dcc448afd56f96bbe933998868be74</id>
<content type='text'>
Introduce gpio_read_bit() for data register read access
and modify sh_gpio_get_value() to make use of the new
function instead of gpio_read_reg(). The purpose of
this change is to update the code to only use the
gpio_read_reg() function for config register access.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: ioremap() support</title>
<updated>2011-12-09T09:07:15Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-12-09T03:14:27Z</published>
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<id>urn:sha1:b0e10211cba1629e2e534ca9cb3d87cfc7e389ea</id>
<content type='text'>
Add support for non-entity mapped PFC registers through
the use of struct resource and ioremap()/iounmap().

The PFC main data structure gets updated with a pointer
to a struct resources array that point out all register
windows used by the PFC instance. The register definitions
are kept as physical addresses but the PFC code will do
transparent conversion into virtual addresses whenever
register windows are specified using with struct resource.

To introduce as little performance penalty as possible the
virtual address of each data register is cached in memory.
The virtual address of each configuration register is however
calculated during run time. This because the configuration
is considered slow path so focus is instead put on keeping
memory foot print as small as possible.

The PFC register access  code is in this patch updated from
__raw_readN() / __raw_writeN() into ioreadN() / iowriteN().

This patch is needed to support the PFC block in r8a7779.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: pfc: Add GPIO IRQ support</title>
<updated>2011-10-28T06:03:52Z</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2011-09-28T07:50:58Z</published>
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<id>urn:sha1:ad2a8e7ea4128af984a98537b1b9484722b6b4bb</id>
<content type='text'>
Add GPIO IRQ support to the shared PFC code in drivers/sh/pfc.c

The enums pointed out by a certain GPIO will be matched against
a table for IRQ to enum mappings.

Only the shared PFC code is updated by this patch. SoC specific
changes are also needed to allow platforms to make use of this
feature.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
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