kernel/drivers/remoteproc/mtk_common.h, branch linux-rolling-lts

remoteproc: mediatek: Support setting DRAM and IPI shared buffer sizes

2024-04-30T16:43:59Z

The SCP on different chips will require different DRAM sizes and IPI shared buffer sizes based on varying requirements. Signed-off-by: Olivia Wen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240430011534.9587-4-olivia.wen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout

2023-09-13T17:46:16Z

The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230901080935.14571-12-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset

2023-09-13T17:46:08Z

Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset" configuration to control the access destination of SCP core 1 to boot core 1 from different SRAM location. The "core 1 SRAM offset" configuration is composed by a range and an offset. It works like a simple memory mapped mechanism. When SCP core 1 accesses a SRAM address located in the range, the SCP bus adds the configured offset to the address to shift the physical destination address on SCP SRAM. This shifting is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230901080935.14571-11-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Remove dependency of MT8195 SCP L2TCM power control on dual-core SCP

2023-09-13T17:45:59Z

Previously, SCP core 0 controlled the power of L2TCM and dictated that SCP core 1 could only boot after SCP core 0. To address this constraint, extracted the power control flow of L2TCM and made it shared between both cores, enabling support for arbitrary boot order. The flow for controlling L2TCM power has been incorporated into the mt8195_scp_before_load() and mt8195_scp_stop() APIs, which are respectively invoked during the rproc->ops->start() and rproc->ops->stop() operations. These APIs effectively serve the same purpose as the rproc prepare()/unprepare() APIs." Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230901080935.14571-10-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Probe SCP cluster on single-core SCP

2023-09-13T17:45:40Z

This is the 3rd preliminary step for probing multi-core SCP. Rewrite the probing flow of single-core SCP to adapt with the 'cluster' concept needed by the multi-core SCP. The SCP core object(s) is maintained at the cluster list. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230901080935.14571-8-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Extract SCP common registers

2023-09-13T17:44:17Z

This is the 1st preliminary steps for probing multi-core SCP. The registers of config and l1tcm are common on single-core SCP and multi-core SCP. Extract these registers out to reduce duplicated fields in mtk_scp when multiple SCP instances are created. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230901080935.14571-6-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Add MT8195 SCP core 1 operations

2023-09-13T17:43:55Z

The SCP rproc driver has a set of chip dependent callbacks for boot sequence and IRQ handling. Implement these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230901080935.14571-5-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Fix side effect of mt8195 sram power on

2022-04-11T15:56:42Z

The definition of L1TCM_SRAM_PDN bits on mt8195 is different to mt8192. L1TCM_SRAM_PDN bits[3:0] control the power of mt8195 L1TCM SRAM. L1TCM_SRAM_PDN bits[7:4] control the access path to EMI for SCP. These bits have to be powered on to allow EMI access for SCP. Bits[7:4] also affect audio DSP because audio DSP and SCP are placed on the same hardware bus. If SCP cannot access EMI, audio DSP is blocked too. L1TCM_SRAM_PDN bits[31:8] are not used. This fix removes modification of bits[7:4] when power on/off mt8195 SCP L1TCM. It's because the modification introduces a short period of time blocking audio DSP to access EMI. This was not a problem until we have to load both SCP module and audio DSP module. audio DSP needs to access EMI because it has source/data on DRAM. Audio DSP will have unexpected behavior when it accesses EMI and the SCP driver blocks the EMI path at the same time. Fixes: 79111df414fc ("remoteproc: mediatek: Support mt8195 scp") Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20220321060340.10975-1-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier

remoteproc: mediatek: Support mt8186 scp

2022-03-11T20:21:43Z

Add SCP support for mt8186 Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220225132747.31808-3-allen-kh.cheng@mediatek.com

remoteproc: mediatek: Support mt8195 scp

2021-09-27T23:37:19Z

The SCP clock design is changed on mt8195 that doesn't need to control SCP clock on kernel side. Signed-off-by: Tinghan Shen Reviewed-by: Mathieu Poirier Link: https://lore.kernel.org/r/20210924033935.2127-5-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier Signed-off-by: Bjorn Andersson