kernel/drivers/pinctrl, branch linux-4.3.y

pinctrl: qcom: ssbi: fix compilation with DEBUG_FS=n

2015-12-09T19:34:32Z

commit 11091fb0a1227d569d09353e1ce1f88694a033dc upstream. The DEBUG_FS=n #defines for the dbg_show functions were missed when renaming the driver from msm_ to pm8xxx_, causing it to break the build when DEBUG_FS isn't enabled: CC [M] drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:597:14: error: â€˜pm8xxx_gpio_dbg_showâ€™ undeclared here (not in a function) .dbg_show = pm8xxx_gpio_dbg_show, Fix this by renaming them correctly. Fixes: b4c45fe974bc ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers") Signed-off-by: Jonas Gorski Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl: uniphier: set input-enable before pin-muxing

2015-12-09T19:34:32Z

commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 upstream. While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada Reported-by: Dai Okamura Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl: uniphier: fix input enable settings for PH1-sLD8

2015-10-02T11:06:26Z

Currently, input enable settings are missing from the PH1-sLD8 pinctrl driver. (All the entries in the pin table are set to UNIPHIER_PIN_IECTRL_NONE). Fill the table with correct values. Fixes: 95372f9dc892 ("pinctrl: UniPhier: add UniPhier PH1-sLD8 pinctrl driver") Signed-off-by: Masahiro Yamada Signed-off-by: Linus Walleij

pinctrl: imx25: ensure that a pin with id i is at position i in the info array

2015-10-02T11:06:02Z

The code in pinctrl-imx.c only works correctly if in the imx_pinctrl_soc_info passed to imx_pinctrl_probe we have: info->pins[i].number = i conf_reg(info->pins[i]) = 4 * i (which conf_reg(pin) being the offset of the pin's configuration register). When the imx25 specific part was introduced in b4a87c9b966f ("pinctrl: pinctrl-imx: add imx25 pinctrl driver") we had: info->pins[i].number = i + 1 conf_reg(info->pins[i]) = 4 * i . Commit 34027ca2bbc6 ("pinctrl: imx25: fix numbering for pins") tried to fix that but made the situation: info->pins[i-1].number = i conf_reg(info->pins[i-1]) = 4 * i which is hardly better but fixed the error seen back then. So insert another reserved entry in the array to finally yield: info->pins[i].number = i conf_reg(info->pins[i]) = 4 * i Fixes: 34027ca2bbc6 ("pinctrl: imx25: fix numbering for pins") Signed-off-by: Uwe Kleine-König Signed-off-by: Linus Walleij

pinctrl: sun5i: Fix a10s pwm1 pinctrl mapping

2015-10-02T11:06:01Z

The comment for PG14 mux setting 3 already correctly states that this muxes PG13 to pwm1, but the text ascociated with it said uart3, fix this. Note that we use "pwm" rather then "pwm1" to be consistent with pwm0 where the mux setting is also simply called "pwm" and to be consistent with sun4i/sun7i which do the same. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2015-09-18T15:11:42Z

Pull irq updates from Thomas Gleixner: "This is a rather large update post rc1 due to the final steps of cleanups and API changes which had to wait for the preparatory patches to hit your tree. - Regression fixes for ARM GIC irqchips - Regression fixes and lockdep anotations for renesas irq chips - The leftovers of the cleanup and preparatory patches which have been ignored by maintainers - Final conversions of the newly merged users of obsolete APIs - Final removal of obsolete APIs - Final removal of ARM artifacts which had been introduced during the conversion of ARM to the generic interrupt code. - Final split of the irq_data into chip specific and common data to reflect the needs of hierarchical irq domains. - Treewide removal of the first argument of interrupt flow handlers, i.e. the irq number, which is not used by the majority of handlers and simple to retrieve from the other argument the irq descriptor. - A few comment updates and build warning fixes" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits) arm64: Remove ununsed set_irq_flags ARM: Remove ununsed set_irq_flags sh: Kill off set_irq_flags usage irqchip: Kill off set_irq_flags usage gpu/drm: Kill off set_irq_flags usage genirq: Remove irq argument from irq flow handlers genirq: Move field 'msi_desc' from irq_data into irq_common_data genirq: Move field 'affinity' from irq_data into irq_common_data genirq: Move field 'handler_data' from irq_data into irq_common_data genirq: Move field 'node' from irq_data into irq_common_data irqchip/gic-v3: Use IRQD_FORWARDED_TO_VCPU flag irqchip/gic: Use IRQD_FORWARDED_TO_VCPU flag genirq: Provide IRQD_FORWARDED_TO_VCPU status flag genirq: Simplify irq_data_to_desc() genirq: Remove __irq_set_handler_locked() pinctrl/pistachio: Use irq_set_handler_locked gpio: vf610: Use irq_set_handler_locked powerpc/mpc8xx: Use irq_set_handler_locked() powerpc/ipic: Use irq_set_handler_locked() powerpc/cpm2: Use irq_set_handler_locked() ...

genirq: Remove irq argument from irq flow handlers

2015-09-16T13:47:51Z

Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Jiang Liu

pinctrl/pistachio: Use irq_set_handler_locked

2015-09-16T13:43:11Z

Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle: Signed-off-by: Thomas Gleixner Cc: Julia Lawall Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org

pinctrl: sunxi: Use irq_set_chip_handler_name_locked()

2015-09-16T10:42:49Z

__irq_set_chip_handler_name_locked() is about to be replaced. Use irq_set_chip_handler_name_locked() instead. Signed-off-by: Thomas Gleixner Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org

pinctrl: samsung: s3c24xx: fix syntax error

2015-09-14T07:13:43Z

?SYNTAX ERROR irq_desc_get_irq_chip() does not exist. It should be irq_desc_get_chip(). Tested by compiling s3c2410_defconfig. Cc: Thomas Gleixner Reported-by: Paul Gortmaker Signed-off-by: Linus Walleij