kernel/drivers/pinctrl, branch linux-4.2.y

pinctrl: baytrail: Use raw_spinlock for locking

2015-11-09T22:37:40Z

commit 78e1c896932df5b8bcdff7bf5417d8e72a4d0d6b upstream. The Intel Baytrail pinctrl driver implements irqchip callbacks which are called with desc->lock raw_spinlock held. In mainline this is fine because spinlock resolves to raw_spinlock. However, running the same code in -rt we get: BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0 Preemption disabled at:[] cpu_startup_entry+0x17f/0x480 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13 ... Call Trace: [] dump_stack+0x4a/0x61 [] ___might_sleep+0xe7/0x170 [] rt_spin_lock+0x1f/0x50 [] byt_gpio_clear_triggering+0x38/0x60 [] byt_irq_mask+0x11/0x20 [] handle_level_irq+0x83/0x150 [] generic_handle_irq+0x27/0x40 [] byt_gpio_irq_handler+0x7f/0xc0 [] handle_irq+0xaa/0x190 ... This is because in -rt spinlocks are preemptible so taking the driver private spinlock in irqchip callbacks causes might_sleep() to trigger. In order to keep -rt happy but at the same time make sure that register accesses get serialized, convert the driver to use raw_spinlock instead. Also shorten the critical section a bit in few places. Suggested-by: Linus Walleij Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij Cc: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

pinctrl: baytrail: Serialize all register access

2015-11-09T22:37:40Z

commit 39ce8150a079e3ae6ed9abf26d7918a558ef7c19 upstream. There is a hardware issue in Intel Baytrail where concurrent GPIO register access might result reads of 0xffffffff and writes might get dropped completely. Prevent this from happening by taking the serializing lock in all places where it is possible that more than one thread might be accessing the hardware concurrently. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij Cc: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

pinctrl: imx25: ensure that a pin with id i is at position i in the info array

2015-10-27T00:53:43Z

commit 9911a2d5e9d14e39692b751929a92cb5a1d9d0e0 upstream. The code in pinctrl-imx.c only works correctly if in the imx_pinctrl_soc_info passed to imx_pinctrl_probe we have: info->pins[i].number = i conf_reg(info->pins[i]) = 4 * i (which conf_reg(pin) being the offset of the pin's configuration register). When the imx25 specific part was introduced in b4a87c9b966f ("pinctrl: pinctrl-imx: add imx25 pinctrl driver") we had: info->pins[i].number = i + 1 conf_reg(info->pins[i]) = 4 * i . Commit 34027ca2bbc6 ("pinctrl: imx25: fix numbering for pins") tried to fix that but made the situation: info->pins[i-1].number = i conf_reg(info->pins[i-1]) = 4 * i which is hardly better but fixed the error seen back then. So insert another reserved entry in the array to finally yield: info->pins[i].number = i conf_reg(info->pins[i]) = 4 * i Fixes: 34027ca2bbc6 ("pinctrl: imx25: fix numbering for pins") Signed-off-by: Uwe Kleine-König Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl: at91: fix null pointer dereference

2015-09-29T17:33:23Z

commit 1ab36387ea4face01aac3560b396b1e2ce07c4ff upstream. Not all gpio banks are necessarily enabled, in the current code this can lead to null pointer dereferences. [ 51.130000] Unable to handle kernel NULL pointer dereference at virtual address 00000058 [ 51.130000] pgd = dee04000 [ 51.130000] [00000058] *pgd=3f66d831, *pte=00000000, *ppte=00000000 [ 51.140000] Internal error: Oops: 17 [#1] ARM [ 51.140000] Modules linked in: [ 51.140000] CPU: 0 PID: 1664 Comm: cat Not tainted 4.1.1+ #6 [ 51.140000] Hardware name: Atmel SAMA5 [ 51.140000] task: df6dd880 ti: dec60000 task.ti: dec60000 [ 51.140000] PC is at at91_pinconf_get+0xb4/0x200 [ 51.140000] LR is at at91_pinconf_get+0xb4/0x200 [ 51.140000] pc : [] lr : [] psr: 600f0013 sp : dec61e48 ip : 600f0013 fp : df522538 [ 51.140000] r10: df52250c r9 : 00000058 r8 : 00000068 [ 51.140000] r7 : 00000000 r6 : df53c910 r5 : 00000000 r4 : dec61e7c [ 51.140000] r3 : 00000000 r2 : c06746d4 r1 : 00000000 r0 : 00000003 [ 51.140000] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 51.140000] Control: 10c53c7d Table: 3ee04059 DAC: 00000015 [ 51.140000] Process cat (pid: 1664, stack limit = 0xdec60208) [ 51.140000] Stack: (0xdec61e48 to 0xdec62000) [ 51.140000] 1e40: 00000358 00000000 df522500 ded15f80 c05a9d08 ded15f80 [ 51.140000] 1e60: 0000048c 00000061 df522500 ded15f80 c05a9d08 c01e7304 ded15f80 00000000 [ 51.140000] 1e80: c01e6008 00000060 0000048c c01e6034 c01e5f6c ded15f80 dec61ec0 00000000 [ 51.140000] 1ea0: 00020000 ded6f280 dec61f80 00000001 00000001 c00ae0b8 b6e80000 ded15fb0 [ 51.140000] 1ec0: 00000000 00000000 df4bc974 00000055 00000800 ded6f280 b6e80000 ded6f280 [ 51.140000] 1ee0: ded6f280 00020000 b6e80000 00000000 00020000 c0090dec c0671e1c dec61fb0 [ 51.140000] 1f00: b6f8b510 00000001 00004201 c000924c 00000000 00000003 00000003 00000000 [ 51.140000] 1f20: df4bc940 00022000 00000022 c066e188 b6e7f000 c00836f4 000b6e7f ded6f280 [ 51.140000] 1f40: ded6f280 b6e80000 dec61f80 ded6f280 00020000 c0091508 00000000 00000003 [ 51.140000] 1f60: 00022000 00000000 00000000 ded6f280 ded6f280 00020000 b6e80000 c0091d9c [ 51.140000] 1f80: 00000000 00000000 ffffffff 00020000 00020000 b6e80000 00000003 c000f124 [ 51.140000] 1fa0: dec60000 c000efa0 00020000 00020000 00000003 b6e80000 00020000 000271c4 [ 51.140000] 1fc0: 00020000 00020000 b6e80000 00000003 7fffe000 00000000 00000000 00020000 [ 51.140000] 1fe0: 00000000 bef50b64 00013835 b6f29c76 400f0030 00000003 00000000 00000000 [ 51.140000] [] (at91_pinconf_get) from [] (at91_pinconf_dbg_show+0x18/0x2c0) [ 51.140000] [] (at91_pinconf_dbg_show) from [] (pinconf_pins_show+0xc8/0xf8) [ 51.140000] [] (pinconf_pins_show) from [] (seq_read+0x1a0/0x464) [ 51.140000] [] (seq_read) from [] (__vfs_read+0x20/0xd0) [ 51.140000] [] (__vfs_read) from [] (vfs_read+0x7c/0x108) [ 51.140000] [] (vfs_read) from [] (SyS_read+0x40/0x94) [ 51.140000] [] (SyS_read) from [] (ret_fast_syscall+0x0/0x3c) [ 51.140000] Code: eb010ec2 e30a0d08 e34c005a eb0ae5a7 (e5993000) [ 51.150000] ---[ end trace fb3c370da3ea4794 ]--- Fixes: a0b957f306fa ("pinctrl: at91: allow to have disabled gpio bank") Signed-off-by: David Dueck Acked-by: Ludovic Desroches Acked-by: Alexandre Belloni Acked-by: Nicolas Ferre Cc: Boris Brezillon Cc: Jean-Christophe PLAGNIOL-VILLARD Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl: mediatek: Fix multiple registration issue.

2015-09-29T17:33:22Z

commit d48c2c02645392483f2b88b050d21ce1db6997b3 upstream. Since our common driver need support main chip and PMU at the same time, that means it will register two pinctrl device, and the pinctrl_desc structure should be used two times. But pinctrl_desc use global static definition, then the latest registered pinctrl device will overwrite the old one's, all members in pinctrl_desc will set to the new one's, such as name, pins and pins numbers, etc. This is a bug. Move pinctrl_desc into mtk_pinctrl, assign new value for each pinctrl device to fix it. Signed-off-by: Hongzhou Yang Reviewed-by: Axel Lin Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

Merge tag 'pinctrl-v4.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2015-07-21T22:27:27Z

Pull pin control fixes from Linus Walleij: "Here are some overly ripe pin control fixes for the v4.2 series. They got delayed because of various crap commits and having to clean and rinse the patch stack a few times. Now they are however looking good. - some dead defines dropped from the Samsung driver, was targeted for -rc2 but got delayed - drop the strict mode from abx500, this was too strict - fix the R-Car sparse IRQs code to work as intended - fix the IRQ code for the pinctrl-single GPIO backend to not enforce threaded IRQs - clear the latched events/IRQs for the Broadcom BCM2835 driver - fix up debugfs for the Freescale imx1 driver - fix a typo bug in the Schmitt Trigger setup in the LPC18xx driver" * tag 'pinctrl-v4.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: lpc18xx: fix schmitt trigger setup Subject: pinctrl: imx1-core: Fix debug output in .pin_config_set callback pinctrl: bcm2835: Clear the event latch register when disabling interrupts pinctrl: single: ensure pcs irq will not be forced threaded sh-pfc: fix sparse GPIOs for R-Car SoCs pinctrl: abx500: remove strict mode pinctrl: samsung: Remove old unused defines

pinctrl: lpc18xx: fix schmitt trigger setup

2015-07-20T09:01:53Z

The param_val variable is what determines if schmitt trigger is enabled on a pin or not. A typo here mean that schmitt trigger was always enabled for standard and i2c pins. Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij

Subject: pinctrl: imx1-core: Fix debug output in .pin_config_set callback

2015-07-20T09:01:53Z

imx1_pinconf_set assumes that the array of pins in struct imx1_pinctrl_soc_info can be indexed by pin id to get the pinctrl_pin_desc for a pin. This used to be correct up to commit 607af165c047 which removed some entries from the array and so made it wrong to access the array by pin id. The result of this bug is a wrong pin name in the output for small pin ids and an oops for the bigger ones. This patch is the result of a discussion that includes patches by Markus Pargmann and Chris Ruehl. Fixes: 607af165c047 ("pinctrl: i.MX27: Remove nonexistent pad definitions") Cc: stable@vger.kernel.org Reported-by: Chris Ruehl Signed-off-by: Uwe Kleine-König Reviewed-by: Markus Pargmann Signed-off-by: Linus Walleij

pinctrl: bcm2835: Clear the event latch register when disabling interrupts

2015-07-20T09:01:52Z

It's possible to hit a race condition if interrupts are generated on a GPIO pin when the IRQ line in question is being disabled. If the interrupt is freed, bcm2835_gpio_irq_disable() is called which disables the event generation sources (edge, level). If an event occurred between the last disabling of hard IRQs and the write to the event source registers, a bit would be set in the GPIO event detect register (GPEDSn) which goes unacknowledged by bcm2835_gpio_irq_handler() so Linux complains loudly. There is no per-GPIO mask register, so when disabling GPIO interrupts write 1 to the relevant bit in GPEDSn to clear out any stale events. Signed-off-by: Jonathan Bell Acked-by: Stephen Warren Signed-off-by: Linus Walleij

pinctrl: single: ensure pcs irq will not be forced threaded

2015-07-20T09:01:52Z

The PSC IRQ is requested using request_irq() API and as result it can be forced to be threaded IRQ in RT-Kernel if PCS_QUIRK_HAS_SHARED_IRQ is enabled for pinctrl domain. As result, following 'possible irq lock inversion dependency' report can be seen: ========================================================= [ INFO: possible irq lock inversion dependency detected ] 3.14.43-rt42-00360-g96ff499-dirty #24 Not tainted --------------------------------------------------------- irq/369-pinctrl/927 just changed the state of lock: (&pcs->lock){+.....}, at: [] pcs_irq_handle+0x48/0x9c but this lock was taken by another, HARDIRQ-safe lock in the past: (&irq_desc_lock_class){-.....} and interrupts could create inverse lock ordering between them. other info that might help us debug this: Possible interrupt unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pcs->lock); local_irq_disable(); lock(&irq_desc_lock_class); lock(&pcs->lock); lock(&irq_desc_lock_class); *** DEADLOCK *** no locks held by irq/369-pinctrl/927. the shortest dependencies between 2nd lock and 1st lock: -> (&irq_desc_lock_class){-.....} ops: 58724 { IN-HARDIRQ-W at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock+0x48/0x58 [] handle_fasteoi_irq+0x24/0x15c [] generic_handle_irq+0x3c/0x4c [] handle_IRQ+0x50/0xa0 [] gic_handle_irq+0x3c/0x6c [] __irq_svc+0x44/0x8c [] arch_cpu_idle+0x40/0x4c [] cpu_startup_entry+0x270/0x2e0 [] rest_init+0xd4/0xe4 [] start_kernel+0x3d0/0x3dc [<80008084>] 0x80008084 INITIAL USE at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock_irqsave+0x54/0x68 [] __irq_get_desc_lock+0x64/0xa4 [] irq_set_chip+0x30/0x78 [] irq_set_chip_and_handler_name+0x24/0x3c [] gic_irq_domain_map+0x48/0xb4 [] irq_domain_associate+0x84/0x1d4 [] irq_create_mapping+0x80/0x11c [] irq_create_of_mapping+0x80/0x120 [] irq_of_parse_and_map+0x34/0x3c [] omap_dm_timer_init_one+0x90/0x30c [] omap5_realtime_timer_init+0x8c/0x48c [] time_init+0x28/0x38 [] start_kernel+0x240/0x3dc [<80008084>] 0x80008084 } ... key at: [] irq_desc_lock_class+0x0/0x8 ... acquired at: [] _raw_spin_lock+0x48/0x58 [] pcs_irq_unmask+0x58/0xa0 [] irq_enable+0x38/0x48 [] irq_startup+0x78/0x7c [] __setup_irq+0x4a8/0x4f4 [] request_threaded_irq+0xb8/0x138 [] omap_8250_startup+0x4c/0x148 [] serial8250_startup+0x24/0x30 [] uart_startup.part.9+0x5c/0x1b4 [] uart_open+0xf4/0x16c [] tty_open+0x170/0x61c [] chrdev_open+0xbc/0x1b4 [] do_dentry_open+0x1e8/0x2bc [] finish_open+0x44/0x5c [] do_last.isra.47+0x710/0xca0 [] path_openat+0xc4/0x640 [] do_filp_open+0x3c/0x98 [] do_sys_open+0x114/0x1d8 [] SyS_open+0x28/0x2c [] kernel_init_freeable+0x168/0x1e4 [] kernel_init+0x1c/0xf8 [] ret_from_fork+0x14/0x20 -> (&pcs->lock){+.....} ops: 65 { HARDIRQ-ON-W at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock+0x48/0x58 [] pcs_irq_handle+0x48/0x9c [] pcs_irq_handler+0x1c/0x28 [] irq_forced_thread_fn+0x30/0x74 [] irq_thread+0x158/0x1c4 [] kthread+0xd4/0xe8 [] ret_from_fork+0x14/0x20 INITIAL USE at: [] lock_acquire+0x9c/0x158 [] _raw_spin_lock_irqsave+0x54/0x68 [] pcs_enable+0x7c/0xe8 [] pinmux_enable_setting+0x178/0x220 [] pinctrl_select_state+0x110/0x194 [] pinctrl_bind_pins+0x7c/0x108 [] driver_probe_device+0x70/0x254 [] __driver_attach+0x9c/0xa0 [] bus_for_each_dev+0x78/0xac [] driver_attach+0x2c/0x30 [] bus_add_driver+0x15c/0x204 [] driver_register+0x88/0x108 [] __platform_driver_register+0x64/0x6c [] omap_hsmmc_driver_init+0x1c/0x20 [] do_one_initcall+0x110/0x170 [] kernel_init_freeable+0x140/0x1e4 [] kernel_init+0x1c/0xf8 [] ret_from_fork+0x14/0x20 } ... key at: [] __key.18572+0x0/0x8 ... acquired at: [] mark_lock+0x388/0x76c [] __lock_acquire+0x6d0/0x1f98 [] lock_acquire+0x9c/0x158 [] _raw_spin_lock+0x48/0x58 [] pcs_irq_handle+0x48/0x9c [] pcs_irq_handler+0x1c/0x28 [] irq_forced_thread_fn+0x30/0x74 [] irq_thread+0x158/0x1c4 [] kthread+0xd4/0xe8 [] ret_from_fork+0x14/0x20 stack backtrace: CPU: 1 PID: 927 Comm: irq/369-pinctrl Not tainted 3.14.43-rt42-00360-g96ff499-dirty #24 [] (unwind_backtrace) from [] (show_stack+0x20/0x24) [] (show_stack) from [] (dump_stack+0x84/0xd0) [] (dump_stack) from [] (print_irq_inversion_bug+0x1d0/0x21c) [] (print_irq_inversion_bug) from [] (check_usage_backwards+0xb4/0x11c) [] (check_usage_backwards) from [] (mark_lock+0x388/0x76c) [] (mark_lock) from [] (__lock_acquire+0x6d0/0x1f98) [] (__lock_acquire) from [] (lock_acquire+0x9c/0x158) [] (lock_acquire) from [] (_raw_spin_lock+0x48/0x58) [] (_raw_spin_lock) from [] (pcs_irq_handle+0x48/0x9c) [] (pcs_irq_handle) from [] (pcs_irq_handler+0x1c/0x28) [] (pcs_irq_handler) from [] (irq_forced_thread_fn+0x30/0x74) [] (irq_forced_thread_fn) from [] (irq_thread+0x158/0x1c4) [] (irq_thread) from [] (kthread+0xd4/0xe8) [] (kthread) from [] (ret_from_fork+0x14/0x20) To fix it use IRQF_NO_THREAD to ensure that pcs irq will not be forced threaded. Cc: Tony Lindgren Cc: Sebastian Andrzej Siewior Signed-off-by: Grygorii Strashko Acked-by: Tony Lindgren Signed-off-by: Linus Walleij