kernel/drivers/pinctrl/sunxi/Kconfig, branch linux-6.9.y

pinctrl: sunxi: Add driver for Allwinner D1

2022-07-18T09:39:33Z

This SoC contains a pinctrl with a new register layout. Use the variant parameter to set the right register offsets. This pinctrl also increases the number of functions per pin from 8 to 16, taking advantage of all 4 bits in the mux config field (so far, only functions 0-8 and 14-15 are used). This increases the maximum possible number of functions. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org Signed-off-by: Linus Walleij

pinctrl: sunxi: Remove reset controller consumers

2022-06-15T13:54:37Z

None of the sunxi pin controllers have a module reset line. All of the SoC documentation, where available, agrees. The bits that would be used for the PIO reset (i.e. matching the order of the clock gate bits) are always reserved, both in the CCU and in the PRCM. And experiments on several SoCs, including the A33, confirm that those reserved bits indeed have no effect. Let's remove this superfluous code and dependency, and also remove the include statement that was copied to the other r_pio drivers. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220531053623.43851-2-samuel@sholland.org Signed-off-by: Linus Walleij

pinctrl: sunxi: Add support for the Allwinner H616-R pin controller

2021-01-21T21:15:46Z

There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.com Signed-off-by: Linus Walleij

pinctrl: sunxi: Add support for the Allwinner H616 pin controller

2021-01-21T21:14:18Z

Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.com Signed-off-by: Linus Walleij

pinctrl: sunxi: add support for the Allwinner A100 pin controller

2020-09-12T10:35:42Z

This commit introduces support for the pin controller on A100. Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46Z

Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman

pinctrl: sunxi: Allow to disable pinctrl drivers

2019-04-04T03:55:54Z

Our pinctrl drivers are consisting of some common code, and big pin tables that are SoC-specific. This is fine in most cases, but when you want to reduce the size of the particular kernel image, those big tables are, well, quite big. We haven't had the option to disable them in the past since they were hidden Kconfig options based on the SoC support. However, that granularity isn't great since we don't have one Kconfig option per-SoC, but rather one by family. Make those options selectable by the user so that they can disable it if needed, while keeping the current default to not change the standard case. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)

2018-11-25T12:49:10Z

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: sunxi: add support for H6 R_PIO pin controller

2018-05-16T12:19:13Z

Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs, which controls the PL and PM pin banks. Add support for it. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Acked-by: Rob Herring Signed-off-by: Linus Walleij

pinctrl: sunxi: add support for the Allwinner H6 main pin controller

2018-03-27T13:09:42Z

The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Reviewed-by: Andre Przywara Acked-by: Maxime Ripard Signed-off-by: Linus Walleij