<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/pinctrl/sh-pfc, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-02-11T13:16:11Z</updated>
<entry>
<title>pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions</title>
<updated>2019-02-11T13:16:11Z</updated>
<author>
<name>Takeshi Kihara</name>
<email>takeshi.kihara.df@renesas.com</email>
</author>
<published>2019-02-09T11:02:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=79dbbdbeccc6784d5e189710adcca750c03d3bd4'/>
<id>urn:sha1:79dbbdbeccc6784d5e189710adcca750c03d3bd4</id>
<content type='text'>
This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77965
SoC.

Based on a similar patch of the R8A7796 PFC driver
by Ramesh Shanmugasundaram &lt;ramesh.shanmugasundaram@bp.renesas.com&gt;.

Signed-off-by: Takeshi Kihara &lt;takeshi.kihara.df@renesas.com&gt;
Signed-off-by: Yoshihiro Kaneko &lt;ykaneko0929@gmail.com&gt;
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions</title>
<updated>2019-02-11T13:16:11Z</updated>
<author>
<name>Takeshi Kihara</name>
<email>takeshi.kihara.df@renesas.com</email>
</author>
<published>2019-02-09T11:01:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=729257d674bc2e68bf051af5c7202d882bccafe0'/>
<id>urn:sha1:729257d674bc2e68bf051af5c7202d882bccafe0</id>
<content type='text'>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A77965 SoC.

Signed-off-by: Takeshi Kihara &lt;takeshi.kihara.df@renesas.com&gt;
Signed-off-by: Yoshihiro Kaneko &lt;ykaneko0929@gmail.com&gt;
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: Validate fixed-size field widths at build time</title>
<updated>2019-02-11T13:11:35Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-01-25T10:56:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5e8588c86d71e78de9e97103324d9127063f18d0'/>
<id>urn:sha1:5e8588c86d71e78de9e97103324d9127063f18d0</id>
<content type='text'>
Add a build-time check, to ensure the register and field widths in
descriptors for config registers with fixed-width fields are sane.
This helps catching bugs early.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups</title>
<updated>2019-02-11T13:11:25Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-01-23T15:51:21Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=0e6e448bdcf896d001a289a6112a704542d51516'/>
<id>urn:sha1:0e6e448bdcf896d001a289a6112a704542d51516</id>
<content type='text'>
There are two pin groups for the FSIC SPDIF signal, but the FSIC pin
group array lists only one, and it refers to a nonexistent group.

Fixes: 2ecd4154c906b7d6 ("sh-pfc: sh73a0: Add FSI pin groups and functions")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group</title>
<updated>2019-02-11T13:11:14Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-01-23T16:14:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b9fd50488b4939ce5b3a026d29e752e17c2d1800'/>
<id>urn:sha1:b9fd50488b4939ce5b3a026d29e752e17c2d1800</id>
<content type='text'>
The vin1_data18_b pin group itself is present, but it is not listed in
the VIN1 pin group array, and thus cannot be selected.

Fixes: 7dd74bb1f058786e ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group</title>
<updated>2019-02-11T13:11:02Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-01-23T16:07:43Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a4b0350047f1b10207e25e72d7cd3f7826e93769'/>
<id>urn:sha1:a4b0350047f1b10207e25e72d7cd3f7826e93769</id>
<content type='text'>
The entry for "scifb2_data_c" in the SCIFB2 pin group array contains a
typo, thus the group cannot be selected.

Fixes: 5088451962389924 ("pinctrl: sh-pfc: r8a7791 PFC support")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: emev2: Add missing pinmux functions</title>
<updated>2019-02-11T13:10:46Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-01-24T12:04:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1ecd8c9cb899ae277e6986ae134635cb1a50f5de'/>
<id>urn:sha1:1ecd8c9cb899ae277e6986ae134635cb1a50f5de</id>
<content type='text'>
The err_rst_reqb, ext_clki, lowpwr, and ref_clko pin groups are present,
but no pinmux functions refer to them, hence they can not be selected.

Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions</title>
<updated>2019-02-05T09:46:48Z</updated>
<author>
<name>Takeshi Kihara</name>
<email>takeshi.kihara.df@renesas.com</email>
</author>
<published>2019-01-25T18:01:44Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fdbbd6b74c9278f65302af113e73cf61d36d3037'/>
<id>urn:sha1:fdbbd6b74c9278f65302af113e73cf61d36d3037</id>
<content type='text'>
This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990
SoC.

Signed-off-by: Takeshi Kihara &lt;takeshi.kihara.df@renesas.com&gt;
Signed-off-by: Yoshihiro Kaneko &lt;ykaneko0929@gmail.com&gt;
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: r8a7778: Fix HSPI pin numbers and names</title>
<updated>2019-01-21T12:25:38Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-01-16T10:48:53Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8e32e881947be98abaa917157fefc4a3319e90af'/>
<id>urn:sha1:8e32e881947be98abaa917157fefc4a3319e90af</id>
<content type='text'>
When declaring the HSPI RX1_B and TX1_B pins, two mistakes were made:
  - the rows and columns in the BGA pin matrix, from which the pin
    numbers are derived, were exchanged,
  - it was not taken into account that pin row labelling skips
    characters I, O, Q, and S.

Fix the order, and the corresponding pin names.

Notes:
  - The actual values of the pin numbers don't really matter (they just
    have to be unique), so the wrong order didn't have any impact,
  - Changing the names of the pins is user-visible, but there are no
    users in (upstream) DTS files.

Fixes: 4f82e3ee724f1712 ("sh-pfc: Support pins not associated with a GPIO port")
Fixes: 09cc76a95802e87d ("sh-pfc: r8a7778: add HSPI pin groups")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions</title>
<updated>2019-01-21T12:25:38Z</updated>
<author>
<name>Takeshi Kihara</name>
<email>takeshi.kihara.df@renesas.com</email>
</author>
<published>2019-01-15T12:01:27Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=16978e7d40f73bed462ca991ce3565d133b0c6cd'/>
<id>urn:sha1:16978e7d40f73bed462ca991ce3565d133b0c6cd</id>
<content type='text'>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara &lt;takeshi.kihara.df@renesas.com&gt;
Signed-off-by: Yoshihiro Kaneko &lt;ykaneko0929@gmail.com&gt;
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
</feed>
