Hosts the 0x221E linux distro kernel. https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y 2019-03-11T18:12:50Z 2019-03-11T18:12:50Z Linus Torvalds torvalds@linux-foundation.org 2019-03-11T18:12:50Z urn:sha1:cf0240a755b8b3df51b0b857b03309a666611d58 Pull pin control updates from Linus Walleij: "This is a calm cycle, not much happened this time around: not even much incremental development. Some three new drivers, that is all. No core changes. New drivers: - NXP (ex Freescale) i.MX 8QM driver. - NXP (ex Freescale) i.MX 8MM driver. - AT91 SAM9X60 subdriver. Improvements: - Support for external interrups (EINT) on Mediatek virtual GPIOs. - Make BCM2835 pin config fully generic. - Lots of Renesas SH-PFC incremental improvements" * tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits) pinctrl: imx: fix scu link errors dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding pinctrl: qcom: spmi-gpio: Reorder debug print pinctrl: nomadik: fix possible object reference leak pinctrl: stm32: return error upon hwspinlock failure pinctrl: stm32: fix memory leak issue pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions pinctrl: sh-pfc: Validate fixed-size field widths at build time pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group pinctrl: sh-pfc: emev2: Add missing pinmux functions pinctrl: sunxi: Support I/O bias voltage setting on A80 pinctrl: ingenic: Add LCD pins for the JZ4725B SoC pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl pinctrl: bcm2835: declare pin config as generic pinctrl: qcom: qcs404: Drop unused UFS_RESET macro dt-bindings: add documentation for slew rate ... 2019-03-08T18:09:53Z Linus Torvalds torvalds@linux-foundation.org 2019-03-08T18:09:53Z urn:sha1:3601fe43e8164f67a8de3de8e988bfcb3a94af46 Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v5.1 cycle: Core changes: - The big change this time around is the irqchip handling in the qualcomm pin controllers, closely coupled with the gpiochip. This rework, in a classic fall-between-the-chairs fashion has been sidestepped for too long. The Qualcomm IRQchips using the SPMI and SSBI transport mechanisms have been rewritten to use hierarchical irqchip. This creates the base from which I intend to gradually pull support for hierarchical irqchips into the gpiolib irqchip helpers to cut down on duplicate code. We have too many hacks in the kernel because people have been working around the missing hierarchical irqchip for years, and once it was there, noone understood it for a while. We are now slowly adapting to using it. This is why this pull requests include changes to MFD, SPMI, IRQchip core and some ARM Device Trees pertaining to the Qualcomm chip family. Since Qualcomm have so many chips and such large deployments it is paramount that this platform gets this right, and now it (hopefully) does. - Core support for pull-up and pull-down configuration, also from the device tree. When a simple GPIO chip supports an "off or on" pull-up or pull-down resistor, we provide a way to set this up using machine descriptors or device tree. If more elaborate control of pull up/down (such as resistance shunt setting) is required, drivers should be phased over to use pin control. We do not yet provide a userspace ABI for this pull up-down setting but I suspect the makers are going to ask for it soon enough. PCA953x is the first user of this new API. - The GPIO mockup driver has been revamped after some discussion improving the IRQ simulator in the process. The idea is to make it possible to use the mockup for both testing and virtual prototyping, e.g. when you do not yet have a GPIO expander to play with but really want to get something to develop code around before hardware is available. It's neat. The blackbox testing usecase is currently making its way into kernelci. - ACPI GPIO core preserves non direction flags when updating flags. - A new device core helper for devm_platform_ioremap_resource() is funneled through the GPIO tree with Greg's ACK. New drivers: - TQ-Systems QTMX86 GPIO controllers (using port-mapped I/O) - Gateworks PLD GPIO driver (vaccumed up from OpenWrt) - AMD G-Series PCH (Platform Controller Hub) GPIO driver. - Fintek F81804 & F81966 subvariants. - PCA953x now supports NXP PCAL6416. Driver improvements: - IRQ support on the Nintendo Wii (Hollywood) GPIO. - get_direction() support for the MVEBU driver. - Set the right output level on SAMA5D2. - Drop the unused irq trigger setting on the Spreadtrum driver. - Wakeup support for PCA953x. - A slew of cleanups in the various Intel drivers" * tag 'gpio-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (110 commits) gpio: gpio-omap: fix level interrupt idling gpio: amd-fch: Set proper output level for direction_output x86: apuv2: remove unused variable gpio: pca953x: Use PCA_LATCH_INT platform/x86: fix PCENGINES_APU2 Kconfig warning gpio: pca953x: Fix dereference of irq data in shutdown gpio: amd-fch: Fix type error found by sparse gpio: amd-fch: Drop const from resource gpio: mxc: add check to return defer probe if clock tree NOT ready gpio: ftgpio: Register per-instance irqchip gpio: ixp4xx: Add DT bindings x86: pcengines apuv2 gpio/leds/keys platform driver gpio: AMD G-Series PCH gpio driver drivers: depend on HAS_IOMEM for devm_platform_ioremap_resource() gpio: tqmx86: Set proper output level for direction_output gpio: sprd: Change to use SoC compatible string gpio: sprd: Use SoC compatible string instead of wildcard string gpio: of: Handle both enable-gpio{,s} gpio: of: Restrict enable-gpio quirk to regulator-gpio gpio: davinci: use devm_platform_ioremap_resource() ... 2019-02-21T12:15:07Z Bjorn Andersson bjorn.andersson@linaro.org 2019-02-19T19:12:53Z urn:sha1:202ba5ebc3af1aec3369b22fe69bfbad6263e704 It's reasonable to expect that people turn to the "gpio" debugfs file to first and foremost learn about the direction and value of a gpio, and second to that about it's pinconf. So reorder the value so each line reads: gpioN: direction value ... This also makes it consistent with the TLMM pinctrl driver's output in the same dump. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-02-21T11:58:31Z Linus Walleij linus.walleij@linaro.org 2019-02-21T11:58:31Z urn:sha1:3dda927fdbaac926c50b550ccb51ed18c184468b 2019-02-14T09:03:04Z Brian Masney masneyb@onstation.org 2019-02-14T01:36:41Z urn:sha1:79890c2ec4860c3b715f89248c51abcc76a1fa39 SSBI GPIOs are numbered 1..ngpio, so the boundary check in pm8xxx_domain_translate() is off by one. This patch corrects that check. Signed-off-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-02-13T08:32:10Z Brian Masney masneyb@onstation.org 2019-02-08T02:16:26Z urn:sha1:9d2b563bc23acfa93e7716b3396fd2f79fa8f0cd ssbi-gpio did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-gpio code to correct this issue. The constant PM8XXX_GPIO_PHYSICAL_OFFSET is introduced to replace the hardcoded '1' that previously existed in two places in this driver to improve code readability. This change was tested on an APQ8060 DragonBoard. Signed-off-by: Brian Masney <masneyb@onstation.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-02-13T08:21:28Z Brian Masney masneyb@onstation.org 2019-02-08T02:16:21Z urn:sha1:86291029e97eaf6a9c2ed43e7968ba8cf9f9f3b7 The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,ssbi-gpio OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. This change was tested on an APQ8060 DragonBoard. Signed-off-by: Brian Masney <masneyb@onstation.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-02-13T08:18:49Z Bjorn Andersson bjorn.andersson@linaro.org 2019-02-12T03:52:05Z urn:sha1:dac7da986ba39e9ff6b078ae15b561c4929edec1 GPIOs on the SPMI PMIC are numbered 1..ngpio, so the boundary check in pmic_gpio_domain_translate() is off by one, correct this. Fixes: ca69e2d165eb ("qcom: spmi-gpio: add support for hierarchical IRQ chip") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-02-11T08:15:04Z Bjorn Andersson bjorn.andersson@linaro.org 2019-01-31T17:29:53Z urn:sha1:a5a08c35d382a5a8da397260c3febb8dff4bdeef The SDC controls live in the south tile, not the north one. Correct this so that we program the right registers. Cc: stable@vger.kernel.org Fixes: 22eb8301dbc1 ("pinctrl: qcom: Add qcs404 pinctrl driver") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-02-08T12:09:04Z Bjorn Andersson bjorn.andersson@linaro.org 2019-01-31T17:38:53Z urn:sha1:f1c894712bbe54b0c1d8a24f1b1bc32e3688d4ff The UFS_RESET macro serves no purpose on QCS404, remove it. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>