kernel/drivers/pinctrl/qcom/Makefile, branch linux-6.9.y

pinctrl: qcom: sm4450: dd SM4450 pinctrl driver

2023-12-20T11:03:03Z

Add pinctrl driver for TLMM block found in SM4450 SoC. Can Guo helped out in reviewing the driver. Reviewed-by: Bjorn Andersson Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add X1E80100 pinctrl driver

2023-11-24T10:22:12Z

Add initial pinctrl driver to support pin configuration with pinctrl framework for X1E80100 SoC. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231117093921.31968-3-quic_sibis@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driver

2023-11-13T14:05:13Z

Add Top Level Mode Multiplexer (pinctrl) support for the SM8650 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-3-0e179c368933@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS

2023-11-13T13:58:02Z

Add driver for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm SM8650 SoC. Notable differences against SM8550 LPASS pin controller: 1. Additional address space for slew rate thus driver uses LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different register. 2. Two new pin mux functions: qca_swr_clk and qca_swr_data Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231027093615.140656-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce SM6115 LPI pinctrl driver

2023-07-26T09:09:47Z

Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM

2023-07-24T19:07:04Z

Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: qcom: Add IPQ5018 pinctrl driver

2023-06-09T07:00:09Z

Add pinctrl definitions for the TLMM of IPQ5018. Reviewed-by: Bjorn Andersson Reviewed-by: Linus Walleij Co-developed-by: Nitheesh Sekar Signed-off-by: Nitheesh Sekar Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Signed-off-by: Sricharan Ramabadhran Link: https://lore.kernel.org/r/20230608122152.3930377-5-quic_srichara@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add SDX75 pincontrol driver

2023-05-29T09:47:57Z

Add initial Qualcomm SDX75 pinctrl driver to support pin configuration with pinctrl framework for SDX75 SoC. While at it, reordering the SDX65 entry. Signed-off-by: Rohit Agarwal Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684425432-10072-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add IPQ9574 pinctrl driver

2023-03-19T21:00:47Z

Add pinctrl definitions for the TLMM of IPQ9574 Reviewed-by: Krzysztof Kozlowski Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya Link: https://lore.kernel.org/r/20230316072940.29137-5-quic_devipriy@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add SM7150 pinctrl driver

2023-03-19T20:51:17Z

Add pinctrl driver for TLMM block found in SM7150 SoC. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20230311212114.108870-3-danila@jiaxyga.com Signed-off-by: Linus Walleij