kernel/drivers/pinctrl/qcom/Kconfig, branch linux-rolling-stable

pinctrl: qcom: sm8350-lpass-lpi: Merge with SC7280 to fix I2S2 and SWR TX pins

2026-02-06T15:57:37Z

commit 1fbe3abb449c5ef2178e1c3e3e8b9a43a7a410ac upstream. Qualcomm SC7280 and SM8350 SoCs have slightly different LPASS audio blocks (v9.4.5 and v9.2), however the LPASS LPI pin controllers are exactly the same. The driver for SM8350 has two issues, which can be fixed by simply moving over to SC7280 driver which has them correct: 1. "i2s2_data_groups" listed twice GPIO12, but should have both GPIO12 and GPIO13, 2. "swr_tx_data_groups" contained GPIO5 for "swr_tx_data2" function, but that function is also available on GPIO14, thus listing it twice is not necessary. OTOH, GPIO5 has also "swr_rx_data1", so selecting swr_rx_data function should not block the TX one. Fixes: be9f6d56381d ("pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman

pinctrl: qcom: Add SDM660 LPASS LPI TLMM

2025-09-10T13:35:42Z

The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses predefined pin_offsets for each pin taken from downstream driver, which does not follow the usual 0x1000 distance between pins and uses an array with predefined offsets that do not follow any regular pattern [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Reviewed-by: Konrad Dybcio Signed-off-by: Richard Acayan Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen Signed-off-by: Linus Walleij

pinctrl: qcom: use generic pin function helpers

2025-09-08T12:22:50Z

With the pinmux core no longer duplicating memory used to store the struct pinfunction objects in .rodata, we can now use the existing infrastructure for storing and looking up pin functions in qualcomm drivers. Remove hand-crafted callbacks. Reviewed-by: Konrad Dybcio Tested-by: Neil Armstrong Signed-off-by: Bartosz Golaszewski Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce SM4250 LPI pinctrl driver

2024-06-26T10:41:07Z

Add support for the pin controller block on SM4250 Low Power Island. Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: sm8650-lpass-lpi: correct Kconfig name

2024-02-21T22:00:57Z

Use proper model name in SM8650 LPASS pin controller Kconfig entry. Cc: Fixes: c4e47673853f ("pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240216102435.89867-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS

2023-11-13T13:58:02Z

Add driver for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm SM8650 SoC. Notable differences against SM8550 LPASS pin controller: 1. Additional address space for slew rate thus driver uses LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different register. 2. Two new pin mux functions: qca_swr_clk and qca_swr_data Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231027093615.140656-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce SM6115 LPI pinctrl driver

2023-07-26T09:09:47Z

Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM

2023-07-24T19:07:04Z

Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: qcom: organize audio drivers in menuconfig

2023-06-09T07:11:32Z

The audio pin controller drivers depend on PINCTRL_LPASS_LPI, but since PINCTRL_LPASS_LPI is not the first entry, they are not displayed in menuconfig as dependent of PINCTRL_LPASS_LPI. Re-order the entries to fix this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230601152026.1182648-8-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: organize main SoC drivers in new Kconfig.msm

2023-06-09T07:10:13Z

In menuconfig, some entries depending on PINCTRL_MSM are indented and expressed as dependening but some not, because of other Kconfig entries in between, Move all main Qualcomm SoC pin controller driver entries into new Kconfig.msm file so they will be nicely ordered in Kconfig file (by CONFIG_ name) and properly indented as PINCTRL_MSM dependency in menuconfig. Functionally this is the same, but since entire file is guarded with "if PINCTRL_MSM" drop this dependency from individual entries. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20230601152026.1182648-7-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij