kernel/drivers/pinctrl/pinctrl-tegra124.c, branch linux-6.2.y

pinctrl: tegra: move Tegra pinctrl drivers to sub-directory

2016-02-05T14:16:43Z

Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada Acked-by: Thierry Reding Signed-off-by: Linus Walleij

pinctrl: tegra: some bits move between registers

2015-03-09T17:10:58Z

Some of the pinmux configuration bits that exist in "drive group" registers in Tegra30..Tegra124 move to the "pinmux" registers on future chips. Add a flag to support this. Signed-off-by: Stephen Warren Tested-by: Alexandre Courbot Signed-off-by: Linus Walleij

pinctrl: tegra: driver layout/consistency fixes

2015-03-09T17:10:57Z

Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by: Stephen Warren Tested-by: Alexandre Courbot Signed-off-by: Linus Walleij

pinctrl: drop owner assignment from platform_drivers

2014-10-20T14:21:21Z

A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang

pinctrl: tegra: Add MIPI pad control

2014-09-19T17:28:54Z

This patch adds MIPI CSI/DSIB pad control mux register from the APB misc block to tegra pinctrl. Without writing to this register, the dsib pads are muxed as csi, and cannot be used. The register is not yet documented in the TRM, here is the description: 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0 [31:02] RESERVED [01:01] DSIB_MODE [CSI=0,DSIB=1] [00:00] RESERVED Signed-off-by: Sean Paul Acked-by: Stephen Warren Signed-off-by: Linus Walleij

pinctrl: Make of_device_id array const

2014-08-29T05:13:04Z

Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Kiran Padwal Acked-by: Thierry Reding Acked-by: Stephen Warren Acked-by: Shawn Guo Signed-off-by: Linus Walleij

pinctrl: tegra: remove fsafe from data tables

2014-04-22T14:50:24Z

The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by: Stephen Warren Acked-by: Laxman Dewangan Signed-off-by: Linus Walleij

pinctrl: tegra: remove redundant data table fields

2014-04-22T14:48:39Z

Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by: Stephen Warren Signed-off-by: Linus Walleij

pinctrl: tegra: fix some mistakes in Tegra124

2014-03-14T15:32:36Z

A couple of pairs of pin group names were swapped in the table. This caused the wrong register to be programmed. Luckily, this had little effect, if any, since the swapped pins were likely to be programmed identically. Signed-off-by: Stephen Warren Signed-off-by: Linus Walleij

pinctrl: tegra: consistency cleanup

2014-03-12T14:27:33Z

Fix Tegra30/114/124 pinmux drivers consistency issues. * Sort all lists of the same object type (e.g. #defines for pins, and the array that defines their names) in the same order. * Whitespace fixes. * Consistency in layout between the 3 drivers. These driver files were also auto-generated, which should allow us to make e.g. the U-Boot drivers completely consistent with the kernel in the future:-) Signed-off-by: Stephen Warren Signed-off-by: Linus Walleij