<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/pinctrl/intel/pinctrl-jasperlake.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2023-11-13T11:33:27Z</updated>
<entry>
<title>pinctrl: jasperlake: Switch to use Intel pin control PM ops</title>
<updated>2023-11-13T11:33:27Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2023-10-30T12:07:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5ce3422e04135680697abb6f8ff577d38173247c'/>
<id>urn:sha1:5ce3422e04135680697abb6f8ff577d38173247c</id>
<content type='text'>
The main driver conditionally exports the PM ops structure.
Switch this driver to use it instead of customly wrapped one.

Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20231030120734.2831419-12-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Switch to use exported namespace</title>
<updated>2023-08-15T16:21:38Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2023-08-15T16:18:58Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=34393c367872a6ef5aaf36172d7238668db23ae4'/>
<id>urn:sha1:34393c367872a6ef5aaf36172d7238668db23ae4</id>
<content type='text'>
We already have a few symbols exported in the namespace.
Let's do the same for others (except PM for now).

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: jasperlake: Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS()</title>
<updated>2022-12-27T19:17:55Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2022-12-19T12:26:37Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6ab57fb3f1f8c6d039f4ba72f404ab5aced1904c'/>
<id>urn:sha1:6ab57fb3f1f8c6d039f4ba72f404ab5aced1904c</id>
<content type='text'>
Use INTEL_COMMUNITY_GPPS() common macro instead custom JSL_COMMUNITY().

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: jasperlake: Fix HOSTSW_OWN offset</title>
<updated>2020-11-16T10:07:57Z</updated>
<author>
<name>Evan Green</name>
<email>evgreen@chromium.org</email>
</author>
<published>2020-11-11T23:17:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=cdd8fc2dd64e3f1b22a6636e242d0eff49c4ba22'/>
<id>urn:sha1:cdd8fc2dd64e3f1b22a6636e242d0eff49c4ba22</id>
<content type='text'>
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.

Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Cc: stable@vger.kernel.org
Signed-off-by: Evan Green &lt;evgreen@chromium.org&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: jasperlake: Unhide SPI group of pins</title>
<updated>2020-11-16T10:07:56Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2020-11-10T19:59:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=59024c936561090d766370e839a880dd42232c33'/>
<id>urn:sha1:59024c936561090d766370e839a880dd42232c33</id>
<content type='text'>
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.

Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support")
Reported-by: Divagar Mohandass &lt;divagar.mohandass@intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add Intel Jasper Lake pin controller support</title>
<updated>2020-04-14T13:17:13Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2020-04-13T11:18:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e278dcb7048b1a27b559e34b0f5f0e50f06221a2'/>
<id>urn:sha1:e278dcb7048b1a27b559e34b0f5f0e50f06221a2</id>
<content type='text'>
This driver adds pinctrl/GPIO support for Intel Jasper Lake SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.

Cc: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
</feed>
