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<title>kernel/drivers/phy/mediatek/phy-mtk-pcie.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y'/>
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<updated>2023-07-17T06:22:56Z</updated>
<entry>
<title>phy: Explicitly include correct DT includes</title>
<updated>2023-07-17T06:22:56Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2023-07-14T17:48:35Z</published>
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<id>urn:sha1:7559e7572c03e433efec7734af6a674fdd83dd68</id>
<content type='text'>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Marc Kleine-Budde &lt;mkl@pengutronix.de&gt; # for drivers/phy/phy-can-transceiver.c
Acked-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Sergio Paracuellos &lt;sergio.paracuellos@gmail.com&gt;
Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: mediatek: pcie: use new helper to update register bits</title>
<updated>2022-09-24T06:27:49Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2022-09-20T09:00:25Z</published>
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<id>urn:sha1:d87f2b83739bdfdb5d2787886e247e5a174b4e90</id>
<content type='text'>
The new helper will use FIELD_PREP() macro to prepare bits value
according to mask, then we no need do it anymore.

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20220920090038.15133-6-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: mediatek: Add PCIe PHY driver</title>
<updated>2022-07-05T05:28:38Z</updated>
<author>
<name>Jianjun Wang</name>
<email>jianjun.wang@mediatek.com</email>
</author>
<published>2022-06-17T07:02:46Z</published>
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<id>urn:sha1:e4e46bc71c18407c087bbade3c92d4554207be21</id>
<content type='text'>
Add PCIe GEN3 PHY driver support on MediaTek chipsets.

Signed-off-by: Jianjun Wang &lt;jianjun.wang@mediatek.com&gt;
Reviewed-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Reviewed-by: AngeloGioachino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20220617070246.20142-3-jianjun.wang@mediatek.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
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