<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/pci/probe.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
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<updated>2019-05-25T16:16:43Z</updated>
<entry>
<title>PCI: Init PCIe feature bits for managed host bridge alloc</title>
<updated>2019-05-25T16:16:43Z</updated>
<author>
<name>Jean-Philippe Brucker</name>
<email>jean-philippe.brucker@arm.com</email>
</author>
<published>2019-03-18T16:07:18Z</published>
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<id>urn:sha1:c1f52d4b8b6e5009a2cd966ebfabd35358b6c02c</id>
<content type='text'>
commit 6302bf3ef78dd210b5ff4a922afcb7d8eff8a211 upstream.

Two functions allocate a host bridge: devm_pci_alloc_host_bridge() and
pci_alloc_host_bridge().  At the moment, only the unmanaged one initializes
the PCIe feature bits, which prevents from using features such as hotplug
or AER on some systems, when booting with device tree.  Make the
initialization code common.

Fixes: 02bfeb484230 ("PCI/portdrv: Simplify PCIe feature permission checking")
Signed-off-by: Jean-Philippe Brucker &lt;jean-philippe.brucker@arm.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: stable@vger.kernel.org	# v4.17+
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>PCI/LINK: Deduplicate bandwidth reports for multi-function devices</title>
<updated>2019-03-25T22:59:07Z</updated>
<author>
<name>Lukas Wunner</name>
<email>lukas@wunner.de</email>
</author>
<published>2019-03-20T11:05:30Z</published>
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<id>urn:sha1:0fa635aec9abd718bd18c0bda2261351a0811efc</id>
<content type='text'>
If a multi-function device's bandwidth is already limited when it is
enumerated, a message is logged only for function 0.  By contrast, when
downtraining occurs after enumeration, a message is logged for all
functions.  That's because the former uses pcie_report_downtraining(),
whereas the latter uses __pcie_print_link_status() (which doesn't filter
functions != 0).  I am seeing this happen on a MacBookPro9,1 with a GPU
(function 0) and an integrated HDA controller (function 1).

Avoid this incongruence by calling pcie_report_downtraining() in both
cases.

Signed-off-by: Lukas Wunner &lt;lukas@wunner.de&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Alexandru Gagniuc &lt;alex.gagniuc@dellteam.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/enumeration'</title>
<updated>2019-03-06T21:30:11Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2019-03-06T21:30:11Z</published>
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<id>urn:sha1:5d130e3dd8b6995e93aeb7a740709a46e7acf5df</id>
<content type='text'>
  - Probe bridge window attributes only once at enumeration-time to fix
    device accesses during rescan (Bjorn Helgaas)

  - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du
    Changbin)

  - Use config header type (not class code) identify bridges more reliably
    (Honghui Zhang)

  - Work around Intel Denverton incorrect Trace Hub BAR size reporting
    (Alexander Shishkin)

* pci/enumeration:
  x86/PCI: Fixup RTIT_BAR of Intel Denverton Trace Hub
  PCI: Rely on config space header type, not class code
  PCI: Make pci_size() return real BAR size
  PCI: Probe bridge window attributes once at enumeration-time
</content>
</entry>
<entry>
<title>Merge branch 'pci/aspm'</title>
<updated>2019-03-06T21:30:09Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2019-03-06T21:30:09Z</published>
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<id>urn:sha1:2fcc19b3410734b1896ba3e9fee1df9036e801fd</id>
<content type='text'>
  - Use Latency Tolerance Reporting if already enabled by platform (Bjorn
    Helgaas)

  - Save/restore LTR info for suspend/resume (Bjorn Helgaas)

* pci/aspm:
  PCI/ASPM: Save LTR Capability for suspend/resume
  PCI/ASPM: Use LTR if already enabled by platform
</content>
</entry>
<entry>
<title>PCI/ASPM: Use LTR if already enabled by platform</title>
<updated>2019-02-09T15:21:03Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2019-01-04T23:59:07Z</published>
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<id>urn:sha1:10ecc818ea7319b5d0d2b4e1aa6a77323e776f76</id>
<content type='text'>
RussianNeuroMancer reported that the Intel 7265 wifi on a Dell Venue 11 Pro
7140 table stopped working after wakeup from suspend and bisected the
problem to 9ab105deb60f ("PCI/ASPM: Disable ASPM L1.2 Substate if we don't
have LTR").  David Ward reported the same problem on a Dell Latitude 7350.

After af8bb9f89838 ("PCI/ACPI: Request LTR control from platform before
using it"), we don't enable LTR unless the platform has granted LTR control
to us.  In addition, we don't notice if the platform had already enabled
LTR itself.

After 9ab105deb60f ("PCI/ASPM: Disable ASPM L1.2 Substate if we don't have
LTR"), we avoid using LTR if we don't think the path to the device has LTR
enabled.

The combination means that if the platform itself enables LTR but declines
to give the OS control over LTR, we unnecessarily avoided using ASPM L1.2.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=201469
Fixes: 9ab105deb60f ("PCI/ASPM: Disable ASPM L1.2 Substate if we don't have LTR")
Fixes: af8bb9f89838 ("PCI/ACPI: Request LTR control from platform before using it")
Reported-by: RussianNeuroMancer &lt;russianneuromancer@ya.ru&gt;
Reported-by: David Ward &lt;david.ward@ll.mit.edu&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: stable@vger.kernel.org	# v4.18+</content>
</entry>
<entry>
<title>PCI: Enable SERR# forwarding for all bridges</title>
<updated>2019-02-02T00:12:55Z</updated>
<author>
<name>Bharat Kumar Gogada</name>
<email>bharat.kumar.gogada@xilinx.com</email>
</author>
<published>2018-11-14T14:47:01Z</published>
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<id>urn:sha1:b4f6dcb9d35688392d668c46e834f72c55900b49</id>
<content type='text'>
As per Figure 6-3 in PCIe r4.0, sec 6.2.6, ERR_ messages will be forwarded
from the secondary interface to the primary interface, if the SERR# Enable
bit in the Bridge Control register is set.

It seems clear that an ACPI hotplug parameter method (_HPP or _HPX) that
tells us to "enable SERR in the command register" (ACPI v6.2, sec 6.2.8,
6.2.9.1) refers to PCI_COMMAND_SERR, which enables reporting of errors by
the function itself.

For bridges, we also interpreted that to mean we should enable
PCI_BRIDGE_CTL_SERR, which enables *forwarding* of errors by the bridge.
But we didn't enable PCI_BRIDGE_CTL_SERR anywhere else, which means we
never enabled it for non-ACPI systems or ACPI systems that didn't supply
hotplug parameters.

That means errors reported below bridges were often never forwarded up to a
Root Port where they could be signaled via AER.

Enable PCI_BRIDGE_CTL_SERR for all bridges so we can get better error
reporting for downstream devices.

Signed-off-by: Bharat Kumar Gogada &lt;bharat.kumar.gogada@xilinx.com&gt;
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Rely on config space header type, not class code</title>
<updated>2019-01-30T16:57:08Z</updated>
<author>
<name>Honghui Zhang</name>
<email>honghui.zhang@mediatek.com</email>
</author>
<published>2018-10-16T10:44:43Z</published>
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<id>urn:sha1:b2fb5cc574695a32361a6c1878816b3d6563aa0f</id>
<content type='text'>
The PCI configuration space header type tells us whether the device is a
bridge, a CardBus bridge, or a normal device, and defines the layout of the
rest of the header (PCI r3.0 sec 6.1, PCIe r4.0 sec 7.5.1.1.9).

When we rely on the header format, e.g., when we're dealing with bridge
windows, we should check the header type, not the class code.  The class
code is loosely related to the header type, but is often incorrect and the
spec doesn't actually require it to be related to the header format.

Suggested-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Honghui Zhang &lt;honghui.zhang@mediatek.com&gt;
[bhelgaas: changelog, keep the PCI_CLASS_BRIDGE_HOST check]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Make pci_size() return real BAR size</title>
<updated>2019-01-30T16:44:18Z</updated>
<author>
<name>Du Changbin</name>
<email>changbin.du@gmail.com</email>
</author>
<published>2018-10-13T00:49:19Z</published>
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<id>urn:sha1:01b37f851ca150554496fd6e79c6d9a67992a2c0</id>
<content type='text'>
Currently, the pci_size() function actually returns 'size-1'.  Make it
return real size to avoid confusion.

Signed-off-by: Du Changbin &lt;changbin.du@gmail.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: Probe bridge window attributes once at enumeration-time</title>
<updated>2019-01-22T18:56:35Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2019-01-19T17:35:04Z</published>
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<id>urn:sha1:51c48b310183ab6ba5419edfc6a8de889cc04521</id>
<content type='text'>
pci_bridge_check_ranges() determines whether a bridge supports the optional
I/O and prefetchable memory windows and sets the flag bits in the bridge
resources.  This *could* be done once during enumeration except that the
resource allocation code completely clears the flag bits, e.g., in the
pci_assign_unassigned_bridge_resources() path.

The problem with pci_bridge_check_ranges() in the resource allocation path
is that we may allocate resources after devices have been claimed by
drivers, and pci_bridge_check_ranges() *changes* the window registers to
determine whether they're writable.  This may break concurrent accesses to
devices behind the bridge.

Add a new pci_read_bridge_windows() to determine whether a bridge supports
the optional windows, call it once during enumeration, remember the
results, and change pci_bridge_check_ranges() so it doesn't touch the
bridge windows but sets the flag bits based on those remembered results.

Link: https://lore.kernel.org/linux-pci/1506151482-113560-1-git-send-email-wangzhou1@hisilicon.com
Link: https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg02082.html
Reported-by: Yandong Xu &lt;xuyandong2@huawei.com&gt;
Tested-by: Yandong Xu &lt;xuyandong2@huawei.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Cc: Sagi Grimberg &lt;sagi@grimberg.me&gt;
Cc: Ofer Hayut &lt;ofer@lightbitslabs.com&gt;
Cc: Roy Shterman &lt;roys@lightbitslabs.com&gt;
Cc: Keith Busch &lt;keith.busch@intel.com&gt;
Cc: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;</content>
</entry>
<entry>
<title>PCI / ACPI: Identify untrusted PCI devices</title>
<updated>2018-12-05T09:01:55Z</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2018-08-16T09:28:48Z</published>
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<id>urn:sha1:617654aae50eb59dd98aa53fb562e850937f4cde</id>
<content type='text'>
A malicious PCI device may use DMA to attack the system. An external
Thunderbolt port is a convenient point to attach such a device. The OS
may use IOMMU to defend against DMA attacks.

Some BIOSes mark these externally facing root ports with this
ACPI _DSD [1]:

  Name (_DSD, Package () {
      ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
      Package () {
          Package () {"ExternalFacingPort", 1},
	  Package () {"UID", 0 }
      }
  })

If we find such a root port, mark it and all its children as untrusted.
The rest of the OS may use this information to enable DMA protection
against malicious devices. For instance the device may be put behind an
IOMMU to keep it from accessing memory outside of what the driver has
allocated for it.

While at it, add a comment on top of prp_guids array explaining the
possible caveat resulting when these GUIDs are treated equivalent.

[1] https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports#identifying-externally-exposed-pcie-root-ports

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Acked-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
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