kernel/drivers/pci/controller, branch linux-6.9.y

PCI: rockchip-ep: Remove wrong mask on subsys_vendor_id

2024-06-21T12:40:34Z

commit 2dba285caba53f309d6060fca911b43d63f41697 upstream. Remove wrong mask on subsys_vendor_id. Both the Vendor ID and Subsystem Vendor ID are u16 variables and are written to a u32 register of the controller. The Subsystem Vendor ID was always 0 because the u16 value was masked incorrectly with GENMASK(31,16) resulting in all lower 16 bits being set to 0 prior to the shift. Remove both masks as they are unnecessary and set the register correctly i.e., the lower 16-bits are the Vendor ID and the upper 16-bits are the Subsystem Vendor ID. This is documented in the RK3399 TRM section 17.6.7.1.17 [kwilczynski: removed unnecesary newline] Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Link: https://lore.kernel.org/linux-pci/20240403144508.489835-1-rick.wertenbroek@gmail.com Signed-off-by: Rick Wertenbroek Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

PCI: tegra194: Fix probe path for Endpoint mode

2024-06-12T09:39:09Z

[ Upstream commit 19326006a21da26532d982254677c892dae8f29b ] Tegra194 PCIe probe path is taking failure path in success case for Endpoint mode. Return success from the switch case instead of going into the failure path. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Link: https://lore.kernel.org/linux-pci/20240408093053.3948634-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar Signed-off-by: Krzysztof Wilczyński Reviewed-by: Jon Hunter Signed-off-by: Sasha Levin

PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host

2024-06-12T09:39:09Z

[ Upstream commit 869bc52534065990cb57013b2bb354c0c1e66c5c ] The DWC glue drivers requiring an active reference clock from the PCIe host for initializing their PCIe EP core, set a flag called 'core_init_notifier' to let DWC driver know that these drivers need a special attention during initialization. In these drivers, access to the hw registers (like DBI) before receiving the active refclk from host will result in access failure and also could cause a whole system hang. But the current DWC EP driver doesn't honor the requirements of the drivers setting 'core_init_notifier' flag and tries to access the DBI registers during dw_pcie_ep_init(). This causes the system hang for glue drivers such as Tegra194 and Qcom EP as they depend on refclk from host and have set the above mentioned flag. To workaround this issue, users of the affected platforms have to maintain the dependency with the PCIe host by booting the PCIe EP after host boot. But this won't provide a good user experience, since PCIe EP is _one_ of the features of those platforms and it doesn't make sense to delay the whole platform booting due to PCIe requiring active refclk. So to fix this issue, let's move all the DBI access from dw_pcie_ep_init() in the DWC EP driver to the dw_pcie_ep_init_complete() API. This API will only be called by the drivers setting 'core_init_notifier' flag once refclk is received from host. For the rest of the drivers that gets the refclk locally, this API will be called within dw_pcie_ep_init(). Link: https://lore.kernel.org/linux-pci/20240327-pci-dbi-rework-v12-1-082625472414@linaro.org Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode") Co-developed-by: Vidya Sagar Signed-off-by: Vidya Sagar Signed-off-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Wilczyński Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Signed-off-by: Sasha Levin

Merge tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

2024-03-14T17:58:27Z

Pull PCI updates from Bjorn Helgaas: "Enumeration: - Consolidate interrupt related code in irq.c (Ilpo Järvinen) - Reduce kernel size by replacing sysfs resource macros with functions (Ilpo Järvinen) - Reduce kernel size by compiling sysfs support only when CONFIG_SYSFS=y (Lukas Wunner) - Avoid using Extended Tags on 3ware-9650SE Root Port to work around an apparent hardware defect (Jörg Wedekind) Resource management: - Fix an MMIO mapping leak in pci_iounmap() (Philipp Stanner) - Move pci_iomap.c and other PCI-specific devres code to drivers/pci (Philipp Stanner) - Consolidate PCI devres code in devres.c (Philipp Stanner) Power management: - Avoid D3cold on Asus B1400 PCI-NVMe bridge, where firmware doesn't know how to return correctly to D0, and remove previous quirk that wasn't as specific (Daniel Drake) - Allow runtime PM when the driver enables it but doesn't need any runtime PM callbacks (Raag Jadav) - Drain runtime-idle callbacks before driver removal to avoid races between .remove() and .runtime_idle(), which caused intermittent page faults when the rtsx .runtime_idle() accessed registers that its .remove() had already unmapped (Rafael J. Wysocki) Virtualization: - Avoid Secondary Bus Reset on LSI FW643 so it can be assigned to VMs with VFIO, e.g., for professional audio software on many Apple machines, at the cost of leaking state between VMs (Edmund Raile) Error handling: - Print all logged TLP Prefixes, not just the first, after AER or DPC errors (Ilpo Järvinen) - Quirk the DPC PIO log size for Intel Raptor Lake Root Ports, which still don't advertise a legal size (Paul Menzel) - Ignore expected DPC Surprise Down errors on hot removal (Smita Koralahalli) - Block runtime suspend while handling AER errors to avoid races that prevent the device form being resumed from D3hot (Stanislaw Gruszka) Peer-to-peer DMA: - Use atomic XA allocation in RCU read section (Christophe JAILLET) ASPM: - Collect bits of ASPM-related code that we need even without CONFIG_PCIEASPM into aspm.c (David E. Box) - Save/restore L1 PM Substates config for suspend/resume (David E. Box) - Update save_save when ASPM config is changed, so a .slot_reset() during error recovery restores the changed config, not the .probe()-time config (Vidya Sagar) Endpoint framework: - Refactor and improve pci_epf_alloc_space() API (Niklas Cassel) - Clean up endpoint BAR descriptions (Niklas Cassel) - Fix ntb_register_device() name leak in error path (Yang Yingliang) - Return actual error code for pci_vntb_probe() failure (Yang Yingliang) Broadcom STB PCIe controller driver: - Fix MDIO write polling, which previously never waited for completion (Jonathan Bell) Cadence PCIe endpoint driver: - Clear the ARI "Next Function Number" of last function (Jasko-EXT Wojciech) Freescale i.MX6 PCIe controller driver: - Simplify by replacing switch statements with function pointers for different hardware variants (Frank Li) - Simplify by using clk_bulk*() API (Frank Li) - Remove redundant DT clock and reg/reg-name details (Frank Li) - Add i.MX95 DT and driver support for both Root Complex and Endpoint mode (Frank Li) Microsoft Hyper-V host bridge driver: - Reduce memory usage by limiting ring buffer size to 16KB instead of 4 pages (Michael Kelley) Qualcomm PCIe controller driver: - Add X1E80100 DT and driver support (Abel Vesa) - Add DT 'required-opps' for SoCs that require a minimum performance level (Johan Hovold) - Make DT 'msi-map-mask' optional, depending on how MSI interrupts are mapped (Johan Hovold) - Disable ASPM L0s for sc8280xp, sa8540p and sa8295p because the PHY configuration isn't tuned correctly for L0s (Johan Hovold) - Split dt-binding qcom,pcie.yaml into qcom,pcie-common.yaml and separate files for SA8775p, SC7280, SC8180X, SC8280XP, SM8150, SM8250, SM8350, SM8450, SM8550 for easier reviewing (Krzysztof Kozlowski) - Enable BDF to SID translation by disabling bypass mode (Manivannan Sadhasivam) - Add endpoint MHI support for Snapdragon SA8775P SoC (Mrinmay Sarkar) Synopsys DesignWare PCIe controller driver: - Allocate 64-bit MSI address if no 32-bit address is available (Ajay Agarwal) - Fix endpoint Resizable BAR to actually advertise the required 1MB size (Niklas Cassel) MicroSemi Switchtec management driver: - Release resources if the .probe() fails (Christophe JAILLET) Miscellaneous: - Make pcie_port_bus_type const (Ricardo B. Marliere)" * tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (77 commits) PCI/ASPM: Update save_state when configuration changes PCI/ASPM: Disable L1 before configuring L1 Substates PCI/ASPM: Call pci_save_ltr_state() from pci_save_pcie_state() PCI/ASPM: Save L1 PM Substates Capability for suspend/resume PCI: hv: Fix ring buffer size calculation PCI: dwc: endpoint: Fix advertised resizable BAR size PCI: cadence: Clear the ARI Capability Next Function Number of the last function PCI: dwc: Strengthen the MSI address allocation logic PCI: brcmstb: Fix broken brcm_pcie_mdio_write() polling PCI: qcom: Add X1E80100 PCIe support dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller PCI: qcom: Enable BDF to SID translation properly PCI/AER: Generalize TLP Header Log reading PCI/AER: Use explicit register size for PCI_ERR_CAP PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p dt-bindings: PCI: qcom: Do not require 'msi-map-mask' dt-bindings: PCI: qcom: Allow 'required-opps' PCI/AER: Block runtime suspend when handling errors PCI/ASPM: Move pci_save_ltr_state() to aspm.c PCI/ASPM: Always build aspm.c ...

Merge branch 'pci/controller/qcom'

2024-03-12T17:14:26Z

- Split dt-binding qcom,pcie.yaml into qcom,pcie-common.yaml and separate files for SA8775p, SC7280, SC8180X, SC8280XP, SM8150, SM8250, SM8350, SM8450, SM8550 for easier reviewing (Krzysztof Kozlowski) - Allow 'required-opps' DT property for SoCs that require a minimum performance level for the power domain (Johan Hovold) - Remove requirement for 'msi-map-mask' DT property since it depends on how MSIs are mapped (Johan Hovold) - Disable ASPM L0s for sc8280xp, sa8540p and sa8295p because their PHY configuration isn't tuned for L0s, which results in many Correctable Errors (Johan Hovold) - Enable BDF to SID translation by disabling bypass mode (Manivannan Sadhasivam) - Add DT binding and driver support for X1E80100 (Abel Vesa) * pci/controller/qcom: PCI: qcom: Add X1E80100 PCIe support dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller PCI: qcom: Enable BDF to SID translation properly PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p dt-bindings: PCI: qcom: Do not require 'msi-map-mask' dt-bindings: PCI: qcom: Allow 'required-opps' dt-bindings: PCI: qcom,pcie-sa8775p: Move SA8775p to dedicated schema dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema dt-bindings: PCI: qcom,pcie-sc8180x: Move SC8180X to dedicated schema dt-bindings: PCI: qcom,pcie-sc8280xp: Move SC8280XP to dedicated schema dt-bindings: PCI: qcom,pcie-sm8350: Move SM8350 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8150: Move SM8150 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8250: Move SM8250 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8450: Move SM8450 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8550: Move SM8550 to dedicated schema

Merge branch 'pci/controller/imx'

2024-03-12T17:14:26Z

- Replace variant switches with drvdata clock descriptions and clk_bulk API (Frank Li) - Replace variant switches with drvdata PHY flag for devm_phy_get() (Frank Li) - Replace variant switches with drvdata HAS_RESET flags for handling resets (Frank Li) - Replace variant switches with drvdata for LTSSM control bits (Frank Li) - Replace variant switches with drvdata for controller Root Complex vs Endpoint modes (Frank Li) - Replace variant switches with drvdata .init_phy() callback pointers (Frank Li) - Drop dt-binding redundant duplicate clock check (Frank Li) - reg/reg-name (Frank Li) - Drop addr_space retrieval code since dw_pcie_ep_init() already does it (Frank Li) - Add epc_features to drvdata (Frank Li) - Add iMX95 Root Complex and Endpoint support and dt-binding compatible strings (Frank Li) * pci/controller/imx: PCI: imx6: Add iMX95 Endpoint (EP) support dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string PCI: imx6: Add epc_features in imx6_pcie_drvdata PCI: imx6: Clean up addr_space retrieval code PCI: imx6: Add iMX95 PCIe Root Complex support dt-bindings: imx6q-pcie: Add imx95 pcie compatible string dt-bindings: imx6q-pcie: Restruct reg and reg-name dt-bindings: imx6q-pcie: Clean up duplicate clocks check PCI: imx6: Simplify switch-case logic by introducing init_phy() callback PCI: imx6: Simplify configure_type() by using mode_off and mode_mask PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET PCI: imx6: Simplify PHY handling by using IMX6_PCIE_FLAG_HAS_PHYDRV PCI: imx6: Simplify clock handling by using clk_bulk*() function

Merge branch 'pci/controller/hyperv'

2024-03-12T17:14:25Z

- Fix ring buffer size at 16KB (not 4 pages), which reduces memory usage by 128KBytes with 64KB pages (Michael Kelley) * pci/controller/hyperv: PCI: hv: Fix ring buffer size calculation

Merge branch 'pci/controller/dwc'

2024-03-12T17:14:25Z

- Fall back to allocating 64-bit MSI DMA address if unable to allocate a 32-bit address (Ajay Agarwal) * pci/controller/dwc: PCI: dwc: endpoint: Fix advertised resizable BAR size PCI: dwc: Strengthen the MSI address allocation logic

Merge branch 'pci/controller/cadence'

2024-03-12T17:14:25Z

- Clear the ARI Capability Next Function Number of the last function (Jasko-EXT Wojciech) * pci/controller/cadence: PCI: cadence: Clear the ARI Capability Next Function Number of the last function

Merge branch 'pci/controller/broadcom'

2024-03-12T17:14:24Z

- Fix polling for MDIO write completion, which previously used the wrong access width so it always indicated "completed" (Jonathan Bell) * pci/controller/broadcom: PCI: brcmstb: Fix broken brcm_pcie_mdio_write() polling