kernel/drivers/pci/controller/dwc/Kconfig, branch linux-6.18.y

Merge branch 'pci/controller/stm32'

2025-10-03T17:13:23Z

- Update pinctrl documentation of initial states and use in runtime suspend/resume (Christian Bruel) - Add pinctrl_pm_select_init_state() for use by stm32 driver, which needs it during resume (Christian Bruel) - Add devicetree bindings and drivers for the STMicroelectronics STM32MP25 in host and endpoint modes (Christian Bruel) * pci/controller/stm32: MAINTAINERS: Add entry for ST STM32MP25 PCIe drivers PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings PCI: stm32: Add PCIe host support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings pinctrl: Add pinctrl_pm_select_init_state helper function Documentation: pinctrl: Describe PM helper functions for standard states.

PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25

2025-10-01T14:54:18Z

Add driver to configure the STM32MP25 SoC PCIe controller based on the DesignWare PCIe core in endpoint mode. Controller support 2.5 and 5 GT/s data rates and uses the common reference clock provided by the host. The PCIe core_clk receives the pipe0_clk from the ComboPHY as input, and the ComboPHY PLL must be locked for pipe0_clk to be ready. Consequently, PCIe core registers cannot be accessed until the ComboPHY is fully initialised and REFCLK is enabled and ready. Signed-off-by: Christian Bruel [mani: reworded description] Signed-off-by: Manivannan Sadhasivam [bhelgaas: squash in https://patch.msgid.link/20250902122641.269725-1-christian.bruel@foss.st.com to remove redundant link_status checks] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20250820075411.1178729-7-christian.bruel@foss.st.com

PCI: stm32: Add PCIe host support for STM32MP25

2025-10-01T14:53:37Z

Add driver for the STM32MP25 SoC PCIe controller based on the DesignWare PCIe core. Controller supports 2.5 and 5 GT/s data rates, MSI via GICv2m, Single Virtual Channel, Single Function and WAKE# GPIO. Signed-off-by: Christian Bruel [mani: reworded description] Signed-off-by: Manivannan Sadhasivam [bhelgaas: squash error handling cleanup from Christophe JAILLET : https://patch.msgid.link/e69ade3edcec4da2d5bfc66e0d03bbcb5a857021.1759169956.git.christophe.jaillet@wanadoo.fr] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20250820075411.1178729-5-christian.bruel@foss.st.com

PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'

2025-09-25T13:03:52Z

In order to enable PCIe ECAM mechanism in DWC driver as per the 'CFG Shift Feature' documented in Designware databook r5.20a, sec 3.10.10.3, prepare the driver to handle the one time iATU setup and creating ECAM window. Signed-off-by: Krishna Chaitanya Chundru [mani: splitted the preparatory code into a separate commit for bisectability] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20250923-controller-dwc-ecam-v10-2-e84390ba75fa@kernel.org

PCI: qcom: Select PCI Power Control Slot driver

2025-08-11T10:30:12Z

Select the pwrctrl driver, which is utilized to manage the power supplies of the devices connected to the standard PCI slots conforming to specification like PCIe CEM. This ensures that the voltage rails of the standard PCI slots on some platforms eg. X1E80100-QCP can be correctly turned on/off if they are described in PCIe Root Port device tree node. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao [mani: reworded subject and description] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20250722091151.1423332-2-quic_wenbyao@quicinc.com

Merge branch 'pci/controller/sophgo'

2025-07-31T21:12:17Z

- Add DT binding and driver for Sophgo SG2044 PCIe controller driver in Root Complex mode (Inochi Amaoto) * pci/controller/sophgo: PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode dt-bindings: pci: Add Sophgo SG2044 PCIe host

Merge branch 'pci/controller/qcom'

2025-07-31T21:12:16Z

- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM implementation (Mayank Rana) - Rename gen_pci_init() to pci_host_common_ecam_create() and export for use by controller drivers (Mayank Rana) - Add DT binding and driver support for SA8255p, which supports ECAM for Configuration Space access (Mayank Rana) - Update DT binding and driver to describe PHYs and per-Root Port resets in a Root Port stanza and deprecate describing them in the host bridge; this makes it possible to support multiple Root Ports in the future (Krishna Chaitanya Chundru) * pci/controller/qcom: PCI: qcom: Add support for parsing the new Root Port binding dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers PCI: dwc: Export DWC MSI controller related APIs

PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode

2025-07-24T21:29:46Z

Add driver support for DesignWare based PCIe controller in SG2044 SoC. The driver currently supports the Root Complex mode. Signed-off-by: Inochi Amaoto [mani: renamed the driver to 'pcie-sophgo.c' and Kconfig fix] Signed-off-by: Manivannan Sadhasivam [bhelgaas: whitespace] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20250504004420.202685-3-inochiama@gmail.com

PCI: dwc: Switch to msi_create_parent_irq_domain()

2025-07-24T21:00:53Z

Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas Reviewed-by: Thomas Gleixner Link: https://patch.msgid.link/04d4a96046490e50139826c16423954e033cdf89.1750858083.git.namcao@linutronix.de

PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex

2025-07-15T18:21:41Z

Add functionality to enable resource management (like clocks, regulators, PHY) through firmware and enumerate ECAM compliant Root Complex on SA8255p SoC, where the PCIe Root Complex is firmware managed and configured into ECAM compliant mode. Signed-off-by: Mayank Rana [mani: minor code cleanups and commit message rewording] Signed-off-by: Manivannan Sadhasivam [bhelgaas: add "ECAM" in comment] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20250616224259.3549811-5-mayank.rana@oss.qualcomm.com