<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/pci/controller/cadence, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
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<updated>2024-03-10T18:33:16Z</updated>
<entry>
<title>PCI: cadence: Clear the ARI Capability Next Function Number of the last function</title>
<updated>2024-03-10T18:33:16Z</updated>
<author>
<name>Jasko-EXT Wojciech</name>
<email>wojciech.jasko-EXT@continental-corporation.com</email>
</author>
<published>2023-12-02T08:50:15Z</published>
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<id>urn:sha1:667a006d73fb7320fc6f414b6fe11a998fcf0c28</id>
<content type='text'>
Next Function Number field in ARI Capability Register for last function
must be zero by default as per the PCIe specification, indicating there
is no next higher number function but that's not happening in our case,
so this patch clears the Next Function Number field for last function
used.

[kwilczynski: white spaces update for one define]
Link: https://lore.kernel.org/linux-pci/20231202085015.3048516-1-s-vadapalli@ti.com
Signed-off-by: Jasko-EXT Wojciech &lt;wojciech.jasko-EXT@continental-corporation.com&gt;
Signed-off-by: Achal Verma &lt;a-verma1@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
Reviewed-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/irq-clean-up'</title>
<updated>2024-01-15T18:10:40Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-01-15T18:10:40Z</published>
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<id>urn:sha1:dc14155d46b58d8bb6e68970b3314118b79497b7</id>
<content type='text'>
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec
  terminology (Bjorn Helgaas)

- Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence,
  designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape,
  mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop
  the redundant pci_epc_irq_type enum with the same values (Damien Le Moal)

- Use "intx" instead of "leg" or "legacy" when describing INTx interrupts
  in endpoint core, endpoint tests, cadence, dra7xx, designware,
  dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4,
  rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal)

* pci/irq-clean-up:
  PCI: xilinx-nwl: Use INTX instead of legacy
  PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler()
  PCI: rockchip-ep: Use INTX instead of legacy
  PCI: uniphier: Use INTX instead of legacy
  PCI: tegra194: Use INTX instead of legacy
  PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler()
  PCI: keystone: Use INTX instead of legacy
  PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()
  PCI: cadence: Use INTX instead of legacy
  PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq()
  misc: pci_endpoint_test: Use INTX instead of LEGACY
  PCI: endpoint: Rename LEGACY to INTX in test function driver
  PCI: endpoint: Use INTX instead of legacy
  PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
  PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
</content>
</entry>
<entry>
<title>PCI: j721e: Make TI J721E depend on ARCH_K3</title>
<updated>2024-01-06T04:51:51Z</updated>
<author>
<name>Peter Robinson</name>
<email>pbrobinson@gmail.com</email>
</author>
<published>2024-01-04T21:39:06Z</published>
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<id>urn:sha1:177c9ac6ab3fa585608a16877b1fa1aad832571c</id>
<content type='text'>
The J721E PCIe is hardware specific to TI SoC parts so add a dependency
on that so it's available for those SoC parts and for compile testing but
not necessarily everyone who enables the Cadence PCIe controller.

Link: https://lore.kernel.org/linux-pci/20240104213910.1426843-1-pbrobinson@gmail.com
Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
</content>
</entry>
<entry>
<title>PCI: j721e: Add TI J784S4 PCIe configuration</title>
<updated>2024-01-06T04:50:49Z</updated>
<author>
<name>Matt Ranostay</name>
<email>mranostay@ti.com</email>
</author>
<published>2023-11-28T05:44:02Z</published>
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<id>urn:sha1:e49ad667815d37dc621ffdfb7302df6a7265bab8</id>
<content type='text'>
Add PCIe configuration for J784S4 SoC platform which has 4x lane
support.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-6-s-vadapalli@ti.com
Tested-by: Achal Verma &lt;a-verma1@ti.com&gt;
Signed-off-by: Matt Ranostay &lt;mranostay@ti.com&gt;
Signed-off-by: Achal Verma &lt;a-verma1@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
Reviewed-by: Roger Quadros &lt;rogerq@kernel.org&gt;
</content>
</entry>
<entry>
<title>PCI: cadence: Use INTX instead of legacy</title>
<updated>2023-12-19T08:36:42Z</updated>
<author>
<name>Damien Le Moal</name>
<email>dlemoal@kernel.org</email>
</author>
<published>2023-11-22T06:03:58Z</published>
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<id>urn:sha1:570e8579761a68d80c29034c291b34cff732d76d</id>
<content type='text'>
In the Cadence endpoint controller driver, rename the function
cdns_pcie_ep_send_legacy_irq() to cdns_pcie_ep_send_intx_irq() to match
the macro PCI_IRQ_INTX name. Related comments and messages mentioning
"legacy" are also changed to refer to "intx".

Link: https://lore.kernel.org/r/20231122060406.14695-9-dlemoal@kernel.org
Signed-off-by: Damien Le Moal &lt;dlemoal@kernel.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions</title>
<updated>2023-12-18T10:55:56Z</updated>
<author>
<name>Damien Le Moal</name>
<email>dlemoal@kernel.org</email>
</author>
<published>2023-11-22T06:03:52Z</published>
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<id>urn:sha1:74955cb8ccc38539f8c029336e07e6b43b6a942e</id>
<content type='text'>
linux/pci.h defines the IRQ flags PCI_IRQ_INTX, PCI_IRQ_MSI and
PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
definitions provided by enum pci_epc_irq_type. This removes the need
for defining this enum type completely.

Link: https://lore.kernel.org/r/20231122060406.14695-3-dlemoal@kernel.org
Signed-off-by: Damien Le Moal &lt;dlemoal@kernel.org&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lpieralisi@kernel.org&gt;
Reviewed-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Acked-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
</content>
</entry>
<entry>
<title>PCI: j721e: Add PCIe 4x lane selection support</title>
<updated>2023-12-13T18:26:51Z</updated>
<author>
<name>Matt Ranostay</name>
<email>mranostay@ti.com</email>
</author>
<published>2023-11-28T05:44:01Z</published>
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<id>urn:sha1:4490f559f75514d5a6f0e729e85235a7be6216bf</id>
<content type='text'>
Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-5-s-vadapalli@ti.com
Signed-off-by: Matt Ranostay &lt;mranostay@ti.com&gt;
Signed-off-by: Achal Verma &lt;a-verma1@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
Reviewed-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Roger Quadros &lt;rogerq@kernel.org&gt;
</content>
</entry>
<entry>
<title>PCI: j721e: Add per platform maximum lane settings</title>
<updated>2023-12-13T18:26:11Z</updated>
<author>
<name>Matt Ranostay</name>
<email>mranostay@ti.com</email>
</author>
<published>2023-11-28T05:44:00Z</published>
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<id>urn:sha1:3ac7f14084f54bff9c31573d1ed59d047a34fe03</id>
<content type='text'>
Various platforms have different maximum amount of lanes that can be
selected. Add max_lanes to struct j721e_pcie to allow for detection of this
which is needed to calculate the needed bitmask size for the possible lane
count.

Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-4-s-vadapalli@ti.com
Signed-off-by: Matt Ranostay &lt;mranostay@ti.com&gt;
Signed-off-by: Achal Verma &lt;a-verma1@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
Reviewed-by: Ravi Gunasekaran &lt;r-gunasekaran@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/field-get'</title>
<updated>2023-10-28T18:31:05Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-28T18:31:05Z</published>
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<id>urn:sha1:5897c174028a6a05169b6ecdbcd20fe4d1a8bcda</id>
<content type='text'>
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
  Järvinen, Bjorn Helgaas)

- Rework DPC control programming for clarity (Ilpo Järvinen)

* pci/field-get:
  PCI/portdrv: Use FIELD_GET()
  PCI/VC: Use FIELD_GET()
  PCI/PTM: Use FIELD_GET()
  PCI/PME: Use FIELD_GET()
  PCI/ATS: Use FIELD_GET()
  PCI/ATS: Show PASID Capability register width in bitmasks
  PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
  PCI: Use FIELD_GET()
  PCI/MSI: Use FIELD_GET/PREP()
  PCI/DPC: Use defines with DPC reason fields
  PCI/DPC: Use defined fields with DPC_CTL register
  PCI/DPC: Use FIELD_GET()
  PCI: hotplug: Use FIELD_GET/PREP()
  PCI: dwc: Use FIELD_GET/PREP()
  PCI: cadence: Use FIELD_GET()
  PCI: Use FIELD_GET() to extract Link Width
  PCI: mvebu: Use FIELD_PREP() with Link Width
  PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields

# Conflicts:
#	drivers/pci/controller/dwc/pcie-tegra194.c
</content>
</entry>
<entry>
<title>PCI: cadence: Use FIELD_GET()</title>
<updated>2023-10-18T16:12:51Z</updated>
<author>
<name>Ilpo Järvinen</name>
<email>ilpo.jarvinen@linux.intel.com</email>
</author>
<published>2023-10-18T11:32:48Z</published>
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<id>urn:sha1:b09d0f98a434bd6b9b9e0fb63bebfcac5e1a679e</id>
<content type='text'>
Convert open-coded variants of PCI field access into FIELD_GET() to
make the code easier to understand.

Link: https://lore.kernel.org/r/20231018113254.17616-2-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
</feed>
