kernel/drivers/pci/controller/cadence/Makefile, branch linux-rolling-stable

PCI: sky1: Add PCIe host support for CIX Sky1

2025-12-02T20:17:55Z

Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence High Performance Architecture (HPA) PCIe core. The controller supports MSI/MSI-X via GICv3, Single Virtual Channel, and Single Function. Signed-off-by: Hans Zhang [mani: moved the PCI ID definitions and squashed Kconfig change] Signed-off-by: Manivannan Sadhasivam [bhelgaas: sort Kconfig menu entry, squash https://lore.kernel.org/r/aSBqp0cglr-Sc8na@stanley.mountain] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20251108140305.1120117-8-hans.zhang@cixtech.com

PCI: cadence: Add support for High Perf Architecture (HPA) controller

2025-12-02T20:17:03Z

Add support for Cadence PCIe RP configuration for High Performance Architecture (HPA) controllers. The Cadence High Performance controllers are the latest PCIe controllers that have support for DMA, optional IDE and updated register set. Add a common library for High Performance Architecture (HPA) PCIe controllers. Signed-off-by: Manikandan K Pillai Signed-off-by: Manivannan Sadhasivam [bhelgaas: squash https://lore.kernel.org/r/20251120093518.2760492-1-jiapeng.chong@linux.alibaba.com, squash https://lore.kernel.org/all/52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com/] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20251108140305.1120117-5-hans.zhang@cixtech.com

PCI: cadence: Move PCIe RP common functions to a separate file

2025-11-14T17:28:30Z

Move the Cadence PCIe controller RP common functions into a separate file. The common library functions are split from legacy PCIe RP controller functions to a separate file. Signed-off-by: Manikandan K Pillai [mani: removed the unused variable] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com

PCI: sg2042: Add Sophgo SG2042 PCIe driver

2025-09-19T18:22:27Z

Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe controller in SG2042 works in host mode only, supporting data rate up to 16 GT/s and lanes up to x16 or x8. Signed-off-by: Chen Wang [mani: reworded description and minor code cleanups] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com

PCI: j721e: Add TI J721E PCIe driver

2020-08-03T13:49:55Z

Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Link: https://lore.kernel.org/r/20200722110317.4744-14-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi

PCI: cadence: Move all files to per-device cadence directory

2019-11-11T14:57:02Z

Cadence core library files may be used by various platform drivers. Add a new directory "cadence" to group all the Cadence core library files and the platforms using Cadence core library. Signed-off-by: Tom Joseph Signed-off-by: Lorenzo Pieralisi Reviewed-by: Andrew Murray