kernel/drivers/nvmem/sunxi_sid.c, branch 0x221E-v0.0.1-v6.19

nvmem: add explicit config option to read old syntax fixed OF cells

2023-10-21T17:19:06Z

Binding for fixed NVMEM cells defined directly as NVMEM device subnodes has been deprecated. It has been replaced by the "fixed-layout" NVMEM layout binding. New syntax is meant to be clearer and should help avoiding imprecise bindings. NVMEM subsystem already supports the new binding. It should be a good idea to limit support for old syntax to existing drivers that actually support & use it (we can't break backward compatibility!). That way we additionally encourage new bindings & drivers to ignore deprecated binding. It wasn't clear (to me) if rtc and w1 code actually uses old syntax fixed cells. I enabled them to don't risk any breakage. Signed-off-by: Rafał Miłecki [for meson-{efuse,mx-efuse}.c] Acked-by: Martin Blumenstingl [for mtk-efuse.c, nvmem/core.c, nvmem-provider.h] Reviewed-by: AngeloGioacchino Del Regno [MT8192, MT8195 Chromebooks] Tested-by: AngeloGioacchino Del Regno [for microchip-otpc.c] Reviewed-by: Claudiu Beznea [SAMA7G5-EK] Tested-by: Claudiu Beznea Acked-by: Jernej Skrabec Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20231020105545.216052-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: Explicitly include correct DT includes

2023-08-23T14:34:01Z

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230823132744.350618-14-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Convert to devm_platform_ioremap_resource()

2023-08-23T14:34:00Z

Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Acked-by: Jernej Skrabec Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230823132744.350618-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Drop the workaround on A64

2023-02-06T18:06:58Z

Now that the SRAM readout code is fixed by using 32-bit accesses, it always returns the same values as register readout, so the A64 variant no longer needs the workaround. This makes the D1 variant structure redundant, so remove it. Signed-off-by: Samuel Holland Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Always use 32-bit MMIO reads

2023-01-28T13:36:28Z

The SID SRAM on at least some SoCs (A64 and D1) returns different values when read with bus cycles narrower than 32 bits. This is not immediately obvious, because memcpy_fromio() uses word-size accesses as long as enough data is being copied. The vendor driver always uses 32-bit MMIO reads, so do the same here. This is faster than the register-based method, which is currently used as a workaround on A64. And it fixes the values returned on D1, where the SRAM method was being used. The special case for the last word is needed to maintain .word_size == 1 for sysfs ABI compatibility, as noted previously in commit de2a3eaea552 ("nvmem: sunxi_sid: Optimize register read-out method"). Fixes: 07ae4fde9efa ("nvmem: sunxi_sid: Add support for D1 variant") Cc: stable@vger.kernel.org Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230127104015.23839-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Add support for D1 variant

2022-02-21T17:00:30Z

D1 has a smaller eFuse block than some other recent SoCs, and it no longer requires a workaround to read the eFuse data. Signed-off-by: Samuel Holland Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220220151527.17216-7-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Set type to OTP

2021-06-11T08:57:52Z

This device currently reports an "Unknown" type in sysfs. Since it is an eFuse hardware device, set its type to OTP. Signed-off-by: Samuel Holland Acked-by: Chen-Yu Tsai Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20210611083348.20170-7-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: fix A64 SID controller support

2019-08-18T10:56:52Z

Like in H3, A64 SID controller doesn't return correct data when using direct access. It appears that on A64, SID needs 8 bytes of word_size. Workaround is to enable read by registers. Signed-off-by: Stefan Mavrodiev Acked-by: Chen-Yu Tsai Tested-by: Vasily Khoruzhick Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20190818093345.29647-4-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Support SID on H6

2019-04-25T17:43:13Z

Add support for H6's SID controller. It supports 4K-bit EFUSE, bigger than before. Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi-sid: convert to SPDX license tags

2019-04-25T17:43:13Z

Updates license to use SPDX-License-Identifier. Acked-by: Maxime Ripard Signed-off-by: Yangtao Li Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman