<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/net/phy/phy-core.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
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<updated>2019-02-17T23:21:38Z</updated>
<entry>
<title>net: phy: improve phy_resolve_aneg_linkmode</title>
<updated>2019-02-17T23:21:38Z</updated>
<author>
<name>Heiner Kallweit</name>
<email>hkallweit1@gmail.com</email>
</author>
<published>2019-02-14T21:15:31Z</published>
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<id>urn:sha1:a2703de7094211a77f458638289381b2955e0a5d</id>
<content type='text'>
We have the settings array of modes which is sorted based on aneg
priority. Instead of checking each mode manually let's simply iterate
over the sorted settings.

Signed-off-by: Heiner Kallweit &lt;hkallweit1@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Move of_set_phy_eee_broken to phy-core.c</title>
<updated>2019-02-14T00:17:53Z</updated>
<author>
<name>Maxime Chevallier</name>
<email>maxime.chevallier@bootlin.com</email>
</author>
<published>2019-02-11T14:25:27Z</published>
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<id>urn:sha1:3feb9b23bf4cbf9f34568035170c6f1c25416523</id>
<content type='text'>
Since of_set_phy_supported was moved to phy-core.c, we can also move
of_set_phy_eee_broken to the same location, so that we have all OF
functions in the same place.

This patch doesn't intend to introduce any change in behaviour.

Signed-off-by: Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Mask-out non-compatible modes when setting the max-speed</title>
<updated>2019-02-14T00:17:53Z</updated>
<author>
<name>Maxime Chevallier</name>
<email>maxime.chevallier@bootlin.com</email>
</author>
<published>2019-02-11T14:25:26Z</published>
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<id>urn:sha1:a4eaed9f9a895b16bb2c54e0ff6b3c99404fec92</id>
<content type='text'>
When setting a PHY's max speed using either the max-speed DT property
or ethtool, we should mask-out all non-compatible modes according to the
settings table, instead of just the 10/100BASET modes.

Signed-off-by: Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;
Suggested-by: Russell King &lt;rmk+kernel@armlinux.org.uk&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: add register modifying helpers returning 1 on change</title>
<updated>2019-02-10T20:53:18Z</updated>
<author>
<name>Heiner Kallweit</name>
<email>hkallweit1@gmail.com</email>
</author>
<published>2019-02-10T18:57:56Z</published>
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<id>urn:sha1:b8554d4f7288f86fb278e0bc7b5b19579bf16b69</id>
<content type='text'>
When modifying registers there are scenarios where we need to know
whether the register content actually changed. This patch adds
new helpers to not break users of the current ones, phy_modify() etc.

Signed-off-by: Heiner Kallweit &lt;hkallweit1@gmail.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: provide full set of accessor functions to MMD registers</title>
<updated>2019-02-06T17:52:43Z</updated>
<author>
<name>Nikita Yushchenko</name>
<email>nikita.yoush@cogentembedded.com</email>
</author>
<published>2019-02-06T06:36:40Z</published>
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<id>urn:sha1:1878f0dcbff0cd07f62602deb160a44d69a8f146</id>
<content type='text'>
This adds full set of locked and unlocked accessor functions to read and
write PHY MMD registers and/or bitfields.

Set of functions exactly matches what is already available for PHY
legacy registers.

Signed-off-by: Nikita Yushchenko &lt;nikita.yoush@cogentembedded.com&gt;
Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: Heiner Kallweit &lt;hkallweit1@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Convert some PHY and MDIO driver files to SPDX headers</title>
<updated>2019-01-23T04:53:08Z</updated>
<author>
<name>Andrew Lunn</name>
<email>andrew@lunn.ch</email>
</author>
<published>2019-01-21T18:05:50Z</published>
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<id>urn:sha1:a2443fd1a54d6ae787157794a2920dd61f50f7f1</id>
<content type='text'>
Where the license text and the MODULE_LICENSE() value agree, convert
to using an SPDX header, removing the license text.

Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Add support for resolving 5G and 2.5G autoneg</title>
<updated>2018-11-11T18:10:02Z</updated>
<author>
<name>Andrew Lunn</name>
<email>andrew@lunn.ch</email>
</author>
<published>2018-11-10T22:43:37Z</published>
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<id>urn:sha1:cb6402fe26358a33e32fb71054b248c76dcfe491</id>
<content type='text'>
Now that 2.5G and 5G can be represented in phydev-&gt;advertising and
phydev-&gt;lp_advertising, add these two links modes as possible
resolutions to auto negotiation.

Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Add more link modes to the settings table</title>
<updated>2018-11-11T18:10:01Z</updated>
<author>
<name>Andrew Lunn</name>
<email>andrew@lunn.ch</email>
</author>
<published>2018-11-10T22:43:36Z</published>
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<id>urn:sha1:3c6b59d6f07c69dbe9d9e0191d158820bdda7f60</id>
<content type='text'>
Now that PHYs and MAC can support more than 32 bit masks, add link
modes which are &gt; 31 to the PHY settings table.

Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Convert u32 phydev-&gt;lp_advertising to linkmode</title>
<updated>2018-11-11T18:10:01Z</updated>
<author>
<name>Andrew Lunn</name>
<email>andrew@lunn.ch</email>
</author>
<published>2018-11-10T22:43:34Z</published>
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<id>urn:sha1:c0ec3c2736774c69bf5c641aea7712132c0f0eba</id>
<content type='text'>
Convert phy drivers to report the link partner advertised modes using
a linkmode bitmap. This allows them to report the higher speeds which
don't fit in a u32.

Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: ethernet: Convert phydev advertize and supported from u32 to link mode</title>
<updated>2018-11-11T18:10:01Z</updated>
<author>
<name>Andrew Lunn</name>
<email>andrew@lunn.ch</email>
</author>
<published>2018-11-10T22:43:33Z</published>
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<id>urn:sha1:3c1bcc8614db10803f1f57ef0295363917448cb2</id>
<content type='text'>
There are a few MAC/PHYs combinations which now support &gt; 1Gbps. These
may need to make use of link modes with bits &gt; 31. Thus their
supported PHY features or advertised features cannot be implemented
using the current bitmap in a u32. Convert to using a linkmode bitmap,
which can support all the currently devices link modes, and is future
proof as more modes are added.

Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
</feed>
