<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/net/phy/Kconfig, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
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<updated>2017-11-08T01:24:14Z</updated>
<entry>
<title>net: phy: leds: Add support for "link" trigger</title>
<updated>2017-11-08T01:24:14Z</updated>
<author>
<name>Maciej S. Szmigiero</name>
<email>mail@maciej.szmigiero.name</email>
</author>
<published>2017-11-01T23:49:18Z</published>
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<id>urn:sha1:3928ee6485a316c8abde7e24c7f82033a1c8d3ae</id>
<content type='text'>
Currently, we create a LED trigger for any link speed known to a PHY.
These triggers only fire when their exact link speed had been negotiated
(they aren't cumulative, that is, they don't fire for "their or any higher"
link speed).

What we are missing, however, is a trigger which will fire on any link
speed known to the PHY. Such trigger can then be used for implementing a
poor man's substitute of the "link" LED on boards that lack it.
Let's add it.

Signed-off-by: Maciej S. Szmigiero &lt;mail@maciej.szmigiero.name&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: DP83822 initial driver submission</title>
<updated>2017-10-11T21:14:32Z</updated>
<author>
<name>Dan Murphy</name>
<email>dmurphy@ti.com</email>
</author>
<published>2017-10-10T17:42:55Z</published>
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<id>urn:sha1:87461f7a58ab694e638ac52afa543b427751a9d0</id>
<content type='text'>
Add support for the TI  DP83822 10/100Mbit ethernet phy.

The DP83822 provides flexibility to connect to a MAC through a
standard MII, RMII or RGMII interface.

In addition the DP83822 needs to be removed from the DP83848 driver
as the WoL support is added here for this device.

Datasheet:
http://www.ti.com/product/DP83822I/datasheet

Signed-off-by: Dan Murphy &lt;dmurphy@ti.com&gt;
Acked-by: Andrew F. Davis &lt;afd@ti.com&gt;
Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>Add a driver for Renesas uPD60620 and uPD60620A PHYs</title>
<updated>2017-10-10T03:49:36Z</updated>
<author>
<name>Bernd Edlinger</name>
<email>bernd.edlinger@hotmail.de</email>
</author>
<published>2017-10-08T13:40:08Z</published>
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<id>urn:sha1:812b5ca7d376e7e008ac0c897d1ef94eb05ddc3b</id>
<content type='text'>
Signed-off-by: Bernd Edlinger &lt;bernd.edlinger@hotmail.de&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Kconfig: Fix PHY infrastructure menu in menuconfig</title>
<updated>2017-09-19T20:46:43Z</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2017-09-18T12:59:20Z</published>
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<id>urn:sha1:6073512cc8e2c48bed5c6625c02c5e4ae50cec34</id>
<content type='text'>
Since the integration of PHYLINK, the configuration option which
used to be under the PHY infrastructure menu in menuconfig ended
up one level up (the network device driver section)

By placing PHYLINK option right after PHYLIB entry, it broke the
way Kconfig used to build the menu. See kconfig-language.txt, section
"Menu structure", 2nd method.

This is fixed by placing the PHYLINK option just before PHYLIB.

Fixes: 9525ae83959b ("phylink: add phylink infrastructure")
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: mdio-mux-mmioreg: Can handle 8/16/32 bits registers</title>
<updated>2017-09-01T17:26:31Z</updated>
<author>
<name>Corentin Labbe</name>
<email>clabbe.montjoie@gmail.com</email>
</author>
<published>2017-09-01T11:56:03Z</published>
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<id>urn:sha1:c642bbbc72d4d5165da7c8477d13791f5943dd05</id>
<content type='text'>
This patch fix an old information that mdio-mux-mmioreg can only handle
8bit registers.
This is not true anymore.

Signed-off-by: Corentin Labbe &lt;clabbe.montjoie@gmail.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Use tab for indentation in Kconfig</title>
<updated>2017-08-14T18:16:24Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2017-08-14T13:43:00Z</published>
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<id>urn:sha1:54161ed4eedeef9442a0a7d3b1a15ad44f8f9831</id>
<content type='text'>
Using tabs instead of space for indentation.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: Add rockchip PHY driver support</title>
<updated>2017-08-11T21:28:58Z</updated>
<author>
<name>David Wu</name>
<email>david.wu@rock-chips.com</email>
</author>
<published>2017-08-10T13:56:40Z</published>
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<id>urn:sha1:baf6ee81406ab806c7db34bd1e9a0a824cb84c71</id>
<content type='text'>
Support integrated ethernet PHY currently.

Signed-off-by: David Wu &lt;david.wu@rock-chips.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfp: add SFP module support</title>
<updated>2017-08-07T03:55:29Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2017-07-25T14:03:39Z</published>
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<id>urn:sha1:73970055450eebc6fc36fd170e56cc45889d0093</id>
<content type='text'>
Add support for SFP hotpluggable modules via sfp-bus and phylink.
This supports both copper and optical SFP modules, which require
different Serdes modes in order to properly negotiate the link.

Optical SFP modules typically require the Serdes link to be talking
1000BaseX mode - this is the gigabit ethernet mode defined by the
802.3 standard.

Copper SFP modules typically integrate a PHY in the module to convert
from Serdes to copper, and the PHY will be configured by the vendor
to either present a 1000BaseX Serdes link (for fixed 1000BaseT) or a
SGMII Serdes link.  However, this is vendor defined, so we instead
detect the PHY, switch the link to SGMII mode, and use traditional
PHY based negotiation.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>phylink: add phylink infrastructure</title>
<updated>2017-08-07T03:55:29Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2017-07-25T14:03:13Z</published>
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<id>urn:sha1:9525ae83959b60c6061fe2f2caabdc8f69a48bc6</id>
<content type='text'>
The link between the ethernet MAC and its PHY has become more complex
as the interface evolves.  This is especially true with serdes links,
where the part of the PHY is effectively integrated into the MAC.

Serdes links can be connected to a variety of devices, including SFF
modules soldered down onto the board with the MAC, a SFP cage with
a hotpluggable SFP module which may contain a PHY or directly modulate
the serdes signals onto optical media with or without a PHY, or even
a classical PHY connection.

Moreover, the negotiation information on serdes links comes in two
varieties - SGMII mode, where the PHY provides its speed/duplex/flow
control information to the MAC, and 1000base-X mode where both ends
exchange their abilities and each resolve the link capabilities.

This means we need a more flexible means to support these arrangements,
particularly with the hotpluggable nature of SFP, where the PHY can
be attached or detached after the network device has been brought up.

Ethtool information can come from multiple sources:
- we may have a PHY operating in either SGMII or 1000base-X mode, in
  which case we take ethtool/mii data directly from the PHY.
- we may have a optical SFP module without a PHY, with the MAC
  operating in 1000base-X mode - the ethtool/mii data needs to come
  from the MAC.
- we may have a copper SFP module with a PHY whic can't be accessed,
  which means we need to take ethtool/mii data from the MAC.

Phylink aims to solve this by providing an intermediary between the
MAC and PHY, providing a safe way for PHYs to be hotplugged, and
allowing a SFP driver to reconfigure the serdes connection.

Phylink also takes over support of fixed link connections, where the
speed/duplex/flow control are fixed, but link status may be controlled
by a GPIO signal.  By avoiding the fixed-phy implementation, phylink
can provide a faster response to link events: fixed-phy has to wait for
phylib to operate its state machine, which can take several seconds.
In comparison, phylink takes milliseconds.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;

- remove sync status
- rework supported and advertisment handling
- add 1000base-x speed for fixed links
- use functionality exported from phy-core, reworking
  __phylink_ethtool_ksettings_set for it
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: phy: add I2C mdio bus</title>
<updated>2017-08-07T03:55:28Z</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2017-07-25T14:03:08Z</published>
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<id>urn:sha1:453d00defba502a48e3f9a218a519b233ff83d16</id>
<content type='text'>
Add an I2C MDIO bus bridge library, to allow phylib to access PHYs which
are connected to an I2C bus instead of the more conventional MDIO bus.
Such PHYs can be found in SFP adapters and SFF modules.

Since PHYs appear at I2C bus address 0x40..0x5f, and 0x50/0x51 are
reserved for SFP EEPROMs/diagnostics, we must not allow the MDIO bus
to access these I2C addresses.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
</feed>
