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<title>kernel/drivers/net/ethernet/sfc/ethtool_common.c, branch linux-5.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.14.y</id>
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<updated>2021-11-06T13:11:28Z</updated>
<entry>
<title>sfc: Fix reading non-legacy supported link modes</title>
<updated>2021-11-06T13:11:28Z</updated>
<author>
<name>Erik Ekman</name>
<email>erik@kryo.se</email>
</author>
<published>2021-10-17T17:16:57Z</published>
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<id>urn:sha1:6467b75cf9d137109579272c03ce631edb0928ee</id>
<content type='text'>
commit 041c61488236a5a84789083e3d9f0a51139b6edf upstream.

Everything except the first 32 bits was lost when the pause flags were
added. This makes the 50000baseCR2 mode flag (bit 34) not appear.

I have tested this with a 10G card (SFN5122F-R7) by modifying it to
return a non-legacy link mode (10000baseCR).

Signed-off-by: Erik Ekman &lt;erik@kryo.se&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>sfc: decouple TXQ type from label</title>
<updated>2020-09-12T00:15:22Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-11T22:39:02Z</published>
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<id>urn:sha1:12804793b17c0e19115a90d98f2f3df0cb79e233</id>
<content type='text'>
Make it possible to have an arbitrary mapping from types to labels,
 because when we add inner-csum-offload TXQs there will no longer be a
 convenient nesting hierarchy of NIC types (EF10 will have inner-csum
 TXQs, while Siena will have HIGHPRI).
Correct a misleading comment on efx_hard_start_xmit().

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: remove EFX_DRIVER_VERSION</title>
<updated>2020-09-07T21:46:13Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-07T16:15:18Z</published>
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<id>urn:sha1:60bd2a2d1f601a7c0efbf8a956f6c920bbee9ad9</id>
<content type='text'>
Per-module versions for in-tree drivers are deprecated.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>sfc: remove phy_op indirection</title>
<updated>2020-09-07T21:46:13Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-07T16:14:34Z</published>
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<id>urn:sha1:c77289b4332eb4f51eef3091142b927ffe5a2a14</id>
<content type='text'>
Originally there were several implementations of PHY operations for the
 several different PHYs used on Falcon boards.  But Falcon is now in a
 separate driver, and all sfc NICs since then have had MCDI-managed PHYs.
Thus, there is no need to indirect through function pointers in
 efx-&gt;phy_op; we can simply call the efx_mcdi_phy_* functions directly.

This also hooks up these functions for EF100, which was previously using
 the dummy_phy_ops.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>sfc: skeleton EF100 PF driver</title>
<updated>2020-07-27T19:26:55Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-27T11:55:55Z</published>
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<id>urn:sha1:51b35a454efdcd86f578e61ec8bf7596299c5f80</id>
<content type='text'>
No TX or RX path, no MCDI, not even an ifup/down handler.
Besides stubs, the bulk of the patch deals with reading the Xilinx
 extended PCIe capability, which tells us where to find our BAR.

Though in the same module, EF100 has its own struct pci_driver,
 which is named sfc_ef100.

A small number of additional nic_type methods are added; those in the
 TX (tx_enqueue) and RX (rx_packet) paths are called through indirect
 call wrappers to minimise the performance impact.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: remove efx_ethtool_nway_reset()</title>
<updated>2020-07-27T19:26:55Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-27T11:54:55Z</published>
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<id>urn:sha1:0ccf267e3477157a91766ca5175b5624936e7491</id>
<content type='text'>
An MDIO-based n-way restart does not make sense for any of the NICs
 supported by this driver, nor for the coming EF100.
Unlike on Falcon (which was already split off into a separate driver),
 the PHY on all of Siena, EF10 and EF100 is managed by MC firmware.
While Siena can talk to the PHY over MDIO, doing so for anything other
 than debugging purposes (mdio_mii_ioctl) is likely to confuse the
 firmware.
(According to the SFC firmware team, this support was originally added
 to the Siena driver early in the development of that product, before
 it was decided to have firmware manage the PHY.)

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: get drvinfo driver name from outside the common code</title>
<updated>2020-07-02T21:47:40Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-02T16:31:43Z</published>
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<id>urn:sha1:bcacac7a8cd9939a991fd20acb1b9f57251363b9</id>
<content type='text'>
Since ethtool_common.o will be built into both sfc and sfc_ef100 drivers,
 it can't use KBUILD_MODNAME directly.  Instead, make it reference a
 string provided by the individual driver code.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: assign TXQs without gaps</title>
<updated>2020-07-02T21:47:40Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-02T16:29:58Z</published>
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<id>urn:sha1:a81dcd85a7c1bc548ce8fb635623970fdee5887d</id>
<content type='text'>
Since we only allocate VIs for the number of TXQs we actually need, we
 cannot naively use "channel * TXQ_TYPES + txq" for the TXQ number, as
 this has gaps (when efx-&gt;tx_queues_per_channel &lt; EFX_TXQ_TYPES) and
 thus overruns the driver's VI allocations, causing the firmware to
 reject the MC_CMD_INIT_TXQ based on INSTANCE.
Thus, we distinguish INSTANCE (stored in tx_queue-&gt;queue) from LABEL
 (tx_queue-&gt;label); the former is allocated starting from 0 in
 efx_set_channels(), while the latter is simply the txq type (index in
 channel-&gt;tx_queue array).
To simplify things, rather than changing tx_queues_per_channel after
 setting up TXQs, make Siena always probe its HIGHPRI queues at start
 of day, rather than deferring it until tc mqprio enables them.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: support setting MTU even if not privileged to configure MAC fully</title>
<updated>2020-07-02T21:47:39Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-02T16:27:35Z</published>
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<id>urn:sha1:af3c38d3fb7c3003842974b1de454ecebbd8bc83</id>
<content type='text'>
Unprivileged functions (such as VFs) may set their MTU by use of the
 'control' field of MC_CMD_SET_MAC_EXT, as used in efx_mcdi_set_mtu().
If calling efx_ef10_mac_reconfigure() from efx_change_mtu(), and the
 NIC supports the above (SET_MAC_ENHANCED capability), use it rather
 than efx_mcdi_set_mac().

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: commonise other ethtool bits</title>
<updated>2020-06-30T00:37:48Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-06-29T13:35:15Z</published>
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<id>urn:sha1:5671dd5565d443185cdc325e8bea0cdd77f3911b</id>
<content type='text'>
A few more ethtool handlers which EF100 will share.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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