<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/net/ethernet/intel/ice/ice_flex_pipe.c, branch linux-6.18.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.18.y</id>
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<updated>2025-10-28T19:49:59Z</updated>
<entry>
<title>ice: fix usage of logical PF id</title>
<updated>2025-10-28T19:49:59Z</updated>
<author>
<name>Grzegorz Nitka</name>
<email>grzegorz.nitka@intel.com</email>
</author>
<published>2025-10-08T10:28:53Z</published>
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<id>urn:sha1:9a0f81fc64b2ba80ce768cd6e680c0f440723464</id>
<content type='text'>
In some devices, the function numbers used are non-contiguous. For
example, here is such configuration for E825 device:

root@/home/root# lspci -v | grep Eth
0a:00.0 Ethernet controller: Intel Corporation Ethernet Connection
E825-C for backplane (rev 04)
0a:00.1 Ethernet controller: Intel Corporation Ethernet Connection
E825-C for backplane (rev 04)
0a:00.4 Ethernet controller: Intel Corporation Ethernet Connection
E825-C 10GbE (rev 04)
0a:00.5 Ethernet controller: Intel Corporation Ethernet Connection
E825-C 10GbE (rev 04)

When distributing RSS and FDIR masks, which are global resources across
the active devices, it is required to have a contiguous PF id, which can
be described as a logical PF id. In the case above, function 0 would
have a logical PF id of 0, function 1 would have a logical PF id
of 1, and functions 4 and 5 would have a logical PF ids 2 and 3
respectively.
Using logical PF id can properly describe which slice of resources can
be used by a particular PF.

The 'function id' to 'logical id' mapping has been introduced with the
commit 015307754a19 ("ice: Support VF queue rate limit and quanta size
configuration"). However, the usage of 'logical_pf_id' field was
unintentionally skipped for profile mask configuration.
Fix it by using 'logical_pf_id' instead of 'pf_id' value when configuring
masks.

Without that patch, wrong indexes, i.e. out of range for given PF, can
be used while configuring resources masks, which might lead to memory
corruption and undefined driver behavior.
The call trace below is one of the examples of such error:

[  +0.000008] WARNING: CPU: 39 PID: 3830 at drivers/base/devres.c:1095
devm_kfree+0x70/0xa0
[  +0.000002] RIP: 0010:devm_kfree+0x70/0xa0
[  +0.000001] Call Trace:
[  +0.000002]  &lt;TASK&gt;
[  +0.000002]  ice_free_hw_tbls+0x183/0x710 [ice]
[  +0.000106]  ice_deinit_hw+0x67/0x90 [ice]
[  +0.000091]  ice_deinit+0x20d/0x2f0 [ice]
[  +0.000076]  ice_remove+0x1fa/0x6a0 [ice]
[  +0.000075]  pci_device_remove+0xa7/0x1d0
[  +0.000010]  device_release_driver_internal+0x365/0x530
[  +0.000006]  driver_detach+0xbb/0x170
[  +0.000003]  bus_remove_driver+0x117/0x290
[  +0.000007]  pci_unregister_driver+0x26/0x250

Fixes: 015307754a19 ("ice: Support VF queue rate limit and quanta size configuration")
Suggested-by: Dan Nowlin &lt;dan.nowlin@intel.com&gt;
Signed-off-by: Grzegorz Nitka &lt;grzegorz.nitka@intel.com&gt;
Reviewed-by: Aleksandr Loktionov &lt;aleksandr.loktionov@intel.com&gt;
Reviewed-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Tested-by: Rinitha S &lt;sx.rinitha@intel.com&gt; (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: convert ice_add_prof() to bitmap</title>
<updated>2025-07-18T16:02:28Z</updated>
<author>
<name>Jesse Brandeburg</name>
<email>jesse.brandeburg@intel.com</email>
</author>
<published>2025-06-18T11:28:53Z</published>
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<id>urn:sha1:850a9a32ab6d8bdd2caf667e184e802aaa2b022d</id>
<content type='text'>
Previously the ice_add_prof() took an array of u8 and looped over it with
for_each_set_bit(), examining each 8 bit value as a bitmap.
This was just hard to understand and unnecessary, and was triggering
undefined behavior sanitizers with unaligned accesses within bitmap
fields (on our internal tools/builds). Since the @ptype being passed in
was already declared as a bitmap, refactor this to use native types with
the advantage of simplifying the code to use a single loop.

Co-developed-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Signed-off-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Signed-off-by: Aleksandr Loktionov &lt;aleksandr.loktionov@intel.com&gt;
CC: Jesse Brandeburg &lt;jbrandeburg@cloudflare.com&gt;
Signed-off-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Reviewed-by: Paul Menzel &lt;pmenzel@molgen.mpg.de&gt;
Tested-by: Rinitha S &lt;sx.rinitha@intel.com&gt; (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: enable FDIR filters from raw binary patterns for VFs</title>
<updated>2024-08-13T21:51:29Z</updated>
<author>
<name>Junfeng Guo</name>
<email>junfeng.guo@intel.com</email>
</author>
<published>2024-07-25T22:08:07Z</published>
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<id>urn:sha1:99f419df8a5c5e1a58822203989f77712d01d410</id>
<content type='text'>
Enable VFs to create FDIR filters from raw binary patterns.
The corresponding processes for raw flow are added in the
Parse / Create / Destroy stages.

Reviewed-by: Marcin Szycik &lt;marcin.szycik@linux.intel.com&gt;
Signed-off-by: Junfeng Guo &lt;junfeng.guo@intel.com&gt;
Co-developed-by: Ahmed Zaki &lt;ahmed.zaki@intel.com&gt;
Signed-off-by: Ahmed Zaki &lt;ahmed.zaki@intel.com&gt;
Tested-by: Rafal Romanowski &lt;rafal.romanowski@intel.com&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: add method to disable FDIR SWAP option</title>
<updated>2024-08-13T21:51:29Z</updated>
<author>
<name>Junfeng Guo</name>
<email>junfeng.guo@intel.com</email>
</author>
<published>2024-07-25T22:08:06Z</published>
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<id>urn:sha1:f217c187ea2eb31500fdea34f595f56433a164f1</id>
<content type='text'>
The SWAP Flag in the FDIR Programming Descriptor doesn't work properly,
it is always set and cannot be unset (hardware bug). Thus, add a method
to effectively disable the FDIR SWAP option by setting the FDSWAP instead
of FDINSET registers.

Reviewed-by: Marcin Szycik &lt;marcin.szycik@linux.intel.com&gt;
Signed-off-by: Junfeng Guo &lt;junfeng.guo@intel.com&gt;
Signed-off-by: Ahmed Zaki &lt;ahmed.zaki@intel.com&gt;
Tested-by: Rafal Romanowski &lt;rafal.romanowski@intel.com&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: field prep conversion</title>
<updated>2023-12-18T19:20:26Z</updated>
<author>
<name>Jesse Brandeburg</name>
<email>jesse.brandeburg@intel.com</email>
</author>
<published>2023-12-06T01:01:05Z</published>
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<id>urn:sha1:23eca34e55586099fd4c6edcd0abd60df9456020</id>
<content type='text'>
Refactor ice driver to use FIELD_PREP(), which reduces lines of code
and adds clarity of intent.

This code was generated by the following coccinelle/spatch script and
then manually repaired.

Several places I changed to OR into a single variable with |= instead of
using a multi-line statement with trailing OR operators, as it
(subjectively) makes the code clearer.

A local variable vmvf_and_timeout was created and used to avoid multiple
logical ORs being __le16 converted, which shortened some lines and makes
the code cleaner.

Also clean up a couple of places where conversions were made to have the
code read more clearly/consistently.

@prep2@
constant shift,mask;
type T;
expression a;
@@
-(((T)(a) &lt;&lt; shift) &amp; mask)
+FIELD_PREP(mask, a)

@prep@
constant shift,mask;
type T;
expression a;
@@
-((T)((a) &lt;&lt; shift) &amp; mask)
+FIELD_PREP(mask, a)

Cc: Julia Lawall &lt;Julia.Lawall@inria.fr&gt;
CC: Alexander Lobakin &lt;aleksander.lobakin@intel.com&gt;
Reviewed-by: Marcin Szycik &lt;marcin.szycik@linux.intel.com&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Signed-off-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Tested-by: Pucha Himasekhar Reddy &lt;himasekharx.reddy.pucha@intel.com&gt; (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: enable symmetric-xor RSS for Toeplitz hash function</title>
<updated>2023-12-14T06:07:17Z</updated>
<author>
<name>Jeff Guo</name>
<email>jia.guo@intel.com</email>
</author>
<published>2023-12-13T00:33:20Z</published>
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<id>urn:sha1:352e9bf238133882dfaebc0dc59a590732a92006</id>
<content type='text'>
Allow the user to set the symmetric Toeplitz hash function via:

    # ethtool -X eth0 hfunc toeplitz symmetric-xor

All existing RSS configurations will be converted to symmetric unless they
have a non-symmetric field (other than IP src/dst and L4 src/dst ports)
used for hashing. The driver will reject a new RSS configuration if such
a field is requested.

The hash function in the E800 NICs is set per-VSI and a specific AQ
command is needed to modify the hash function. Use the AQ command to
enable setting the symmetric Toeplitz RSS hash function for any VSI
in the new ice_set_rss_hfunc().

When the Symmetric Toeplitz hash function is used, the hardware sets the
input set of the RSS (Toeplitz) algorithm to be the XOR of the fields
index by HSYMM and the fields index by the INSET registers. We use this
to create a symmetric hash by setting the HSYMM registers to point to
their counterparts in the INSET registers:

 HSYMM [src_fv] = dst_fv;
 HSYMM [dst_fv] = src_fv;

where src_fv and dst_fv are the indexes of the protocol's src and dst
fields.

Reviewed-by: Wojciech Drewek &lt;wojciech.drewek@intel.com&gt;
Signed-off-by: Jeff Guo &lt;jia.guo@intel.com&gt;
Signed-off-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Co-developed-by: Ahmed Zaki &lt;ahmed.zaki@intel.com&gt;
Signed-off-by: Ahmed Zaki &lt;ahmed.zaki@intel.com&gt;
Link: https://lore.kernel.org/r/20231213003321.605376-8-ahmed.zaki@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: refactor the FD and RSS flow ID generation</title>
<updated>2023-12-14T06:07:17Z</updated>
<author>
<name>Ahmed Zaki</name>
<email>ahmed.zaki@intel.com</email>
</author>
<published>2023-12-13T00:33:19Z</published>
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<id>urn:sha1:b1f5921a99ac8dedadf1f2599486b2ca9e01cc0f</id>
<content type='text'>
The flow director and RSS blocks use separate methods to generate a
unique 64 bit ID for the flow. This is not extendable, especially for
the RSS that already uses all 64 bit space.

Refactor the flow generation API so that the ID is generated within
ice_flow_add_prof(). The FD and RSS blocks caches the generated ID for
later use.

Suggested-by: Dan Nowlin &lt;dan.nowlin@intel.com&gt;
Reviewed-by: Wojciech Drewek &lt;wojciech.drewek@intel.com&gt;
Signed-off-by: Ahmed Zaki &lt;ahmed.zaki@intel.com&gt;
Link: https://lore.kernel.org/r/20231213003321.605376-7-ahmed.zaki@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: Reduce scope of variables</title>
<updated>2023-01-19T16:18:03Z</updated>
<author>
<name>Tony Nguyen</name>
<email>anthony.l.nguyen@intel.com</email>
</author>
<published>2022-11-23T16:56:40Z</published>
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<id>urn:sha1:bd557d97978ea3e22653117a39184b5db70c7093</id>
<content type='text'>
There are some places where the scope of a variable can
be reduced, so do that.

Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
Tested-by: Gurucharan G &lt;gurucharanx.g@intel.com&gt; (A Contingent worker at Intel)
</content>
</entry>
<entry>
<title>ice: Move support DDP code out of ice_flex_pipe.c</title>
<updated>2023-01-19T16:18:03Z</updated>
<author>
<name>Sergey Temerkhanov</name>
<email>sergey.temerkhanov@intel.com</email>
</author>
<published>2022-12-20T15:01:14Z</published>
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<id>urn:sha1:2ffd87d38d6b9dd8575e4b763ead7127c2695bcb</id>
<content type='text'>
Currently, ice_flex_pipe.c includes the DDP loading functions
and has grown large. Although flexible processing support
code is related to DDP loading, these parts are distinct.
Move the DDP loading functionality from ice_flex_pipe.c to
a separate file.

Signed-off-by: Sergey Temerkhanov &lt;sergey.temerkhanov@intel.com&gt;
Tested-by: Gurucharan G &lt;gurucharanx.g@intel.com&gt; (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: Remove cppcheck suppressions</title>
<updated>2023-01-19T16:18:03Z</updated>
<author>
<name>Tony Nguyen</name>
<email>anthony.l.nguyen@intel.com</email>
</author>
<published>2022-11-23T16:56:27Z</published>
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<id>urn:sha1:df2a4c3f653088c20e7c998acbd959338631f1d8</id>
<content type='text'>
The use of suppressions for cppcheck in the kernel does not look to be
standard as the ice driver is the only one doing it. Remove the
comments/suppressions.

Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
</feed>
