<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/net/ethernet/intel/i40evf, branch linux-4.3.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.3.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.3.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2015-10-07T11:13:50Z</updated>
<entry>
<title>i40e/i40evf: set AQ count after memory allocation</title>
<updated>2015-10-07T11:13:50Z</updated>
<author>
<name>Mitch Williams</name>
<email>mitch.a.williams@intel.com</email>
</author>
<published>2015-10-04T00:13:05Z</published>
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<id>urn:sha1:90d2c056bd85bbb47104c52e08eecf8408163a54</id>
<content type='text'>
The standard way to check if the AQ is enabled is to look at the
count field. So we should only set this field after we have
successfully allocated memory. To do otherwise is to incite
panic among the populace.

Signed-off-by: Mitch Williams &lt;mitch.a.williams@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: check for stopped admin queue</title>
<updated>2015-09-29T03:57:14Z</updated>
<author>
<name>Mitch Williams</name>
<email>mitch.a.williams@intel.com</email>
</author>
<published>2015-09-29T00:31:26Z</published>
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<id>urn:sha1:43ae93a93e8c95c5e6389dc8e11704712b1ab2e9</id>
<content type='text'>
It's possible that while we are waiting for the spinlock, another
entity (that owns the spinlock) has shut down the admin queue.
If we then attempt to use the queue, we will panic.

Add a check for this condition on the receive side. This matches
an existing check on the send queue side.

Signed-off-by: Mitch Williams &lt;mitch.a.williams@intel.com&gt;
Acked-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: Bump i40e to 1.3.9 and i40evf to 1.3.5</title>
<updated>2015-08-26T22:14:36Z</updated>
<author>
<name>Catherine Sullivan</name>
<email>catherine.sullivan@intel.com</email>
</author>
<published>2015-07-10T23:36:10Z</published>
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<id>urn:sha1:bf41846edf5b1618a37f8ec830251b31d8ed6ab3</id>
<content type='text'>
Bump version and update the copyright year for i40evf.

Change-ID: Iddb81b9dba09f0dc57ab54937b5821ecdd721ff6
Signed-off-by: Catherine Sullivan &lt;catherine.sullivan@intel.com&gt;
Tested-by: Andrew Bowers &lt;andrewx.bowers@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: Cache the CEE TLV status returned from firmware</title>
<updated>2015-08-26T22:12:16Z</updated>
<author>
<name>Neerav Parikh</name>
<email>neerav.parikh@intel.com</email>
</author>
<published>2015-07-10T23:36:09Z</published>
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<id>urn:sha1:9fffa3f34dff2585ae86cd5b59c68ad2d4172f25</id>
<content type='text'>
Store the CEE TLV status returned by firmware to allow drivers to dump that
for debug purposes.

Change-ID: Ie3c4cf8cebabee4f15e1e3fdc4fc8a68bbca40ee
Signed-off-by: Neerav Parikh &lt;neerav.parikh@intel.com&gt;
Tested-by: Andrew Bowers &lt;andrewx.bowers@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: add VIRTCHNL_VF_OFFLOAD flag</title>
<updated>2015-08-26T22:09:54Z</updated>
<author>
<name>Anjali Singhai Jain</name>
<email>anjali.singhai@intel.com</email>
</author>
<published>2015-07-10T23:36:08Z</published>
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<id>urn:sha1:b8262a6dfad8825e0b117fe5e3a1715a585bbd79</id>
<content type='text'>
Add virtual channel offload capability to support RX polling mode in the
VF.

Change-ID: Ib643ae2a7506dfc75fc489fc207493fabefa4832
Signed-off-by: Jingjing Wu &lt;jingjing.wu@intel.com&gt;
Signed-off-by: Anjali Singhai Jain &lt;anjali.singhai@intel.com&gt;
Tested-by: Andrew Bowers &lt;andrewx.bowers@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40evf: Remove PF specific register definitions from the VF</title>
<updated>2015-08-26T22:05:17Z</updated>
<author>
<name>Anjali Singhai Jain</name>
<email>anjali.singhai@intel.com</email>
</author>
<published>2015-07-10T23:36:06Z</published>
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<id>urn:sha1:e02a7f83d84d0580a62df8d4c4e95cd8791c6645</id>
<content type='text'>
There were quite a few issues when the wrong defines were getting used
in the VF driver. This patch fixes the code where PF driver registers
were getting used for VF driver, and also removes the registers that are
not being used from the VF register file.

Change-ID: If116a9730112950d006eb8ec763998fc914cc839
Signed-off-by: Anjali Singhai Jain &lt;anjali.singhai@intel.com&gt;
Acked-by: Mitch Williams &lt;mitch.a.williams@intel.com&gt;
Tested-by: Andrew Bowers &lt;andrewx.bowers@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40evf: Use the correct defines to match the VF registers</title>
<updated>2015-08-26T22:02:59Z</updated>
<author>
<name>Anjali Singhai Jain</name>
<email>anjali.singhai@intel.com</email>
</author>
<published>2015-07-10T23:36:05Z</published>
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<id>urn:sha1:b1f3366b86a9e99f4d4d557b02e0f53fa7ccd72c</id>
<content type='text'>
Use CTLN1 instead of CTLN for the VF relative register space.

Change-ID: Iefba63faf0307af55fec8dbb64f26059f7d91318
Signed-off-by: Anjali Singhai Jain &lt;anjali.singhai@intel.com&gt;
Tested-by: Andrew Bowers &lt;andrewx.bowers@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: Add capability to gather VEB per TC stats</title>
<updated>2015-08-26T21:56:08Z</updated>
<author>
<name>Neerav Parikh</name>
<email>neerav.parikh@intel.com</email>
</author>
<published>2015-07-10T23:36:02Z</published>
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<id>urn:sha1:fe860afb4638f5e62e7d861bfc35a1580fb633bb</id>
<content type='text'>
This patch adds capability to update per VEB per TC statistics and dump
it via ethtool. It also adds a structure to hold VEB per TC statistics.
The fields can be filled by reading the GLVEBTC_* counters.

Change-ID: I28b4759b9ab6ad5a61f046a1bc9ef6b16fe31538
Signed-off-by: Neerav Parikh &lt;neerav.parikh@intel.com&gt;
Tested-by: Andrew Bowers &lt;andrewx.bowers@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: Add TX/RX outer UDP checksum support for X722</title>
<updated>2015-08-05T23:53:45Z</updated>
<author>
<name>Anjali Singhai Jain</name>
<email>anjali.singhai@intel.com</email>
</author>
<published>2015-06-05T16:20:31Z</published>
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<id>urn:sha1:527274c78ea7e0cad8b44ea25509c42aa605634e</id>
<content type='text'>
X722 supports offloading of outer UDP TX and RX checksum for tunneled
packets. This patch exposes the support and leaves it enabled by
default.

Signed-off-by: Anjali Singhai Jain &lt;anjali.singhai@intel.com&gt;
Signed-off-by: Catherine Sullivan &lt;catherine.sullivan@intel.com&gt;
Tested-by: Jim Young &lt;james.m.young@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
<entry>
<title>i40e/i40evf: Add support for writeback on ITR feature for X722</title>
<updated>2015-08-05T23:53:45Z</updated>
<author>
<name>Anjali Singhai Jain</name>
<email>anjali.singhai@intel.com</email>
</author>
<published>2015-06-05T16:20:30Z</published>
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<id>urn:sha1:8e0764b4d6be42459b6f517e199b8c7df43cc15c</id>
<content type='text'>
X722 fixes an issue from X710 where TX descriptor WB would not happen if
the interrupts were disabled. In order for the write backs to happen a
bit needs to be set in the dynamic interrupt control register called
WB_ON_ITR. With this feature, the SW driver need not arm SW interrupts to
work around the issue in X710.

Signed-off-by: Anjali Singhai Jain &lt;anjali.singhai@intel.com&gt;
Signed-off-by: Catherine Sullivan &lt;catherine.sullivan@intel.com&gt;
Tested-by: Jim Young &lt;james.m.young@intel.com&gt;
Signed-off-by: Jeff Kirsher &lt;jeffrey.t.kirsher@intel.com&gt;
</content>
</entry>
</feed>
