kernel/drivers/net/ethernet/freescale/fec_ptp.c, branch linux-4.3.y

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

2015-08-01T06:52:20Z

Conflicts: arch/s390/net/bpf_jit_comp.c drivers/net/ethernet/ti/netcp_ethss.c net/bridge/br_multicast.c net/ipv4/ip_fragment.c All four conflicts were cases of simple overlapping changes. Signed-off-by: David S. Miller

net: fec: introduce fec_ptp_stop and use in probe fail path

2015-07-27T04:51:53Z

This function frees resources and cancels delayed work item that have been initialized in fec_ptp_init(). Use this to do proper error handling if something goes wrong in probe function after fec_ptp_init has been called. Signed-off-by: Lucas Stach Acked-by: Fugang Duan Signed-off-by: David S. Miller

freescale: remove incorrect copied comment

2015-07-18T02:59:05Z

The comment in question is word-for-word copied from ixgbe, and clearly has no meaning in freescale's driver. (it even says 'return an error' when the code clearly does not). Remove the comment as it is obviously incorrect and not applicable to the code as it is today. CC: Pantelis Antoniou CC: Vitaly Bordug CC: Signed-off-by: Jacob Keller Acked-by: Richard Cochran Signed-off-by: Jeff Kirsher

net: fec: ptp: correct the ENET_ATCOR value

2015-06-07T22:30:42Z

The current driver adjust freq formula is: fe * diff = ppb * pc Note: fe: ENET ref clock frequency in Hz diff = inc_corr - inc: difference between default increment and correction increment ppb: parts per billion adjustment from base pc: correction period (in number of fe clock cycles) The correction increment will be used after N cycles of regular increments, not every N cycles (with N being the correction period). For example, set ENET_ATCOR=4, INC=8, INC_CORR=9, there will be 4 increments of 8 (ENET_ATINC[INC]) , followed by 1 increment of 9 (ENET_ATINC[INC_CORR]). So, the correct formula is: fe * diff = ppb * (pc + 1) For ENET_ATCOR, a value 0 disables the correction counter and no corrections occur. So base on the origin formula, set pc = pc > 1 ? pc - 1 : pc. Signed-off-by: Fugang Duan Signed-off-by: Frank Li Signed-off-by: David S. Miller

ptp: fec: use helpers for converting ns to timespec.

2015-03-31T21:19:19Z

This patch changes the driver to use ns_to_timespec64() and timespec64_to_ns() instead of open coding the same logic. Compile tested only. Signed-off-by: Richard Cochran Signed-off-by: David S. Miller

ptp: fec: convert to the 64 bit get/set time methods.

2015-03-31T16:01:17Z

This driver's clock is implemented using a timecounter, and so with this patch the driver is ready for the year 2038. Compile tested only. Signed-off-by: Richard Cochran Signed-off-by: David S. Miller

ethernet: codespell comment spelling fixes

2015-03-09T02:54:22Z

To test a checkpatch spelling patch, I ran codespell against drivers/net/ethernet/. $ git ls-files drivers/net/ethernet/ | \ while read file ; do \ codespell -w $file; \ done I removed a false positive in e1000_hw.h Signed-off-by: Joe Perches Signed-off-by: David S. Miller

net: fec: convert to timecounter adjtime.

2014-12-30T23:29:26Z

This patch changes the driver to use the new and improved method for adjusting the offset of a timecounter. Compile tested only. Signed-off-by: Richard Cochran Signed-off-by: David S. Miller

net: fec: ptp: fix convergence issue to support LinuxPTP stack

2014-10-15T20:40:11Z

iMX6SX IEEE 1588 module has one hw issue in capturing the ATVR register. The current SW flow is: ENET0->ATCR |= ENET_ATCR_CAPTURE_MASK; ts_counter_ns = ENET0->ATVR; The ATVR value is not expected value that cause LinuxPTP stack cannot be convergent. ENET Block Guide/ Chapter for the iMX6SX (PELE) address the issue: After set ENET_ATCR[Capture], there need some time cycles before the counter value is capture in the register clock domain. The wait-time-cycles is at least 6 clock cycles of the slower clock between the register clock and the 1588 clock. So need something like: ENET0->ATCR |= ENET_ATCR_CAPTURE_MASK; wait(); ts_counter_ns = ENET0->ATVR; For iMX6SX, the 1588 ts_clk is fixed to 25Mhz, register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns (40ns * 6). The patch add 1us delay before cpu read ATVR register. Changes V2: Modify the commit/comments log to describe the issue clearly. Signed-off-by: Fugang Duan Acked-by: Richard Cochran Signed-off-by: David S. Miller

net: fec: ptp: Enable PPS output based on ptp clock

2014-10-14T18:45:08Z

FEC ptp timer has 4 channel compare/trigger function. It can be used to enable pps output. The pulse would be ouput high exactly on N second. The pulse ouput high on compare event mode is used to produce pulse per second. The pulse width would be one cycle based on ptp timer clock source.Since 31-bit ptp hardware timer is used, the timer will wrap more than 2 seconds. We need to reload the compare compare event about every 1 second. Signed-off-by: Luwei Zhou Signed-off-by: David S. Miller