kernel/drivers/net/dsa/microchip/lan937x.h, branch linux-6.9.y

net: dsa: microchip: add support for credit based shaper

2023-01-24T06:12:35Z

KSZ9477, KSZ9567, KSZ9563, KSZ8563 and LAN937x supports Credit based shaper. To differentiate the chip supporting cbs, tc_cbs_supported flag is introduced in ksz_chip_data. And KSZ series has 16bit Credit increment registers whereas LAN937x has 24bit register. The value to be programmed in the credit increment is determined using the successive multiplication method to convert decimal fraction to hexadecimal fraction. For example: if idleslope is 10000 and sendslope is -90000, then bandwidth is 10000 - (-90000) = 100000. The 10% bandwidth of 100Mbps means 10/100 = 0.1(decimal). This value has to be converted to hexa. 1) 0.1 * 16 = 1.6 --> fraction 0.6 Carry = 1 (MSB) 2) 0.6 * 16 = 9.6 --> fraction 0.6 Carry = 9 3) 0.6 * 16 = 9.6 --> fraction 0.6 Carry = 9 4) 0.6 * 16 = 9.6 --> fraction 0.6 Carry = 9 5) 0.6 * 16 = 9.6 --> fraction 0.6 Carry = 9 6) 0.6 * 16 = 9.6 --> fraction 0.6 Carry = 9 (LSB) Now 0.1(decimal) becomes 0.199999(Hex). If it is LAN937x, 24 bit value will be programmed to Credit Inc register, 0x199999. For others 16 bit value will be prgrammed, 0x1999. Signed-off-by: Arun Ramadoss Signed-off-by: Jakub Kicinski

net: dsa: microchip: add the support for set_ageing_time

2022-09-16T20:51:47Z

KSZ9477 has the 11 bit ageing count value which is split across the two registers. And LAN937x has the 20 bit ageing count which is also split into two registers. Each count in the registers represents 1 second. This patch add the support for ageing time for KSZ9477 and LAN937x series of switch. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: lan937x: add interrupt support for port phy link

2022-09-05T12:06:40Z

This patch enables the interrupts for internal phy link detection for LAN937x. The interrupt enable bits are active low. There is global interrupt mask for each port. And each port has the individual interrupt mask for TAS. QCI, SGMII, PTP, PHY and ACL. The first level of interrupt domain is registered for global port interrupt and second level of interrupt domain for the individual port interrupts. The phy interrupt is enabled in the lan937x_mdio_register function. Interrupt from which port is raised will be detected based on the interrupt host data. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: allow to pass return values for PHY read/write accesses

2022-08-31T08:41:19Z

PHY access may end with errors on different levels. So, allow to forward return values where possible. Signed-off-by: Oleksij Rempel Reviewed-by: Vladimir Oltean Signed-off-by: David S. Miller

net: dsa: microchip: add support for phylink mac config

2022-07-27T08:39:17Z

This patch add support for phylink mac config for ksz series of switches. All the files ksz8795, ksz9477 and lan937x uses the ksz common xmii function. Instead of calling from the individual files, it is moved to the ksz common phylink mac config function. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config

2022-07-27T08:39:17Z

This patch read the rgmii tx and rx delay from device tree and stored it in the ksz_port. It applies the rgmii delay to the xmii tune adjust register based on the interface selected in phylink mac config. There are two rgmii port in LAN937x and value to be loaded in the register vary depends on the port selected. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: add support for common phylink mac link up

2022-07-27T08:39:17Z

This patch add the support for common phylink mac link up for the ksz series switch. The register address, bit position and values are configured based on the chip id to the dev->info structure. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: lan937x: add phylink_mac_config support

2022-07-02T15:34:05Z

This patch add support for phylink_mac_config dsa hook. It configures the mac for MII/RMII modes. The RGMII mode will be added in the future patches. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: lan937x: add phylink_mac_link_up support

2022-07-02T15:34:05Z

This patch add support for phylink_mac_link_up. It configures the mac for the speed, flow control and duplex mode. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller

net: dsa: microchip: lan937x: add phylink_get_caps support

2022-07-02T15:34:05Z

The internal phy of the LAN937x are capable of 100Mbps Full duplex. The xMII port of switch is capable of 10Mbps Full & Half Duplex, 100Mbps Full & Half Duplex and 1000Mbps Half duplex. xMII port also supports Tx and Rx Flow control. Signed-off-by: Arun Ramadoss Signed-off-by: David S. Miller