kernel/drivers/mtd/nand/raw, branch linux-rolling-stable

mtd: rawnand: pl353: Fix software ECC support

2026-03-04T12:21:34Z

[ Upstream commit 89b831ebdaca0df4ca3b226f7e7a1d1db1629060 ] We need to set also write_page_raw in ecc structure to allow choosing SW ECC instead of HW one, otherwise write operation fail. Fixes: 08d8c62164a322 ("mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller") Signed-off-by: Andrea Scian Cc: stable@kernel.org Signed-off-by: Miquel Raynal Signed-off-by: Sasha Levin

mtd: rawnand: cadence: Fix return type of CDMA send-and-wait helper

2026-02-26T23:01:16Z

[ Upstream commit 6d8226cbbf124bb5613b532216b74c886a4361b7 ] cadence_nand_cdma_send_and_wait() propagates negative errno values from cadence_nand_cdma_send(), returns -ETIMEDOUT on failure and -EIO when the CDMA engine reports a command failure. However, it is declared as u32, causing error codes to wrap. Change the return type to int to correctly propagate errors. Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subsystem") Signed-off-by: Alok Tiwari Signed-off-by: Miquel Raynal Signed-off-by: Sasha Levin

treewide: Update email address

2026-01-11T16:09:11Z

In a vain attempt to consolidate the email zoo switch everything to the kernel.org account. Signed-off-by: Thomas Gleixner Signed-off-by: Linus Torvalds

Merge tag 'mtd/for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

2025-12-04T19:07:46Z

Pull mtd updates from Miquel Raynal: "Core MTD changes: - We must ignore error -ENOENT from parsers on subpartitions which is a legitimate return value - PM support is added to the intel-dg driver Raw NAND changes: - The major change in this is the support for the Allwinner H616 NAND controller, which lead to numerous changes and cleanups in the driver. - Another notable change in this driver is the use of field_get() and field_prep(), but since the global support for this helpers is going to be merged in the same release as we start using these helpers, we undefine them in the first place to avoid warnings. - Marvell drivers layout handling changes have also landed, they fix previous definitions and abuses that have been made previously, which implied to relax the ECC parameters validation in the core a bit. - The Cadence NAND controller driver gets NV-DDR interface support. SPI NAND changes: - Support for FudanMicro FM25S01BI3 and ESMT F50L1G41LC is added. SPI NOR changes: - Fix SMPT parsing for S25FS-S flash family. They report variable dummy cycles for reads. This results in the default of 0 being used. This works for other Infineon chips, but not for the S25FS-S family. They need 8 dummy cycles. Add fixup hooks to specify that. Also add fixup hooks to fix incorrect map ID data in SFDP. - Add support for a bunch of Winbond flashes. Their block protection information is not discoverable, so they need to have an entry in the flash tables to describe that. - Some cleanups for Micron flash support. - Add support for Micron mt35xu01gbba. - Some SPI controllers like the Intel one on the PCI bus do not support the read CR opcode (0x35). Do not use the opcode if the controller does not support it. Aside from these main changes, there is the usual load of API updates, kdoc fixes, potential memory leaks fixes, etc" * tag 'mtd/for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (51 commits) mtd: sm_ftl: Fix typo in comment in sm_read_lba mtd: sm_ftl: Replace deprecated strncpy with sysfs_emit in sm_attr_show mtd: lpddr_cmds: fix signed shifts in lpddr_cmds mtd: docg3: fix kernel-doc warnings mtd: spinand: add support for FudanMicro FM25S01BI3 mtd: rawnand: renesas: Handle devm_pm_runtime_enable() errors mtd: nand: realtek-ecc: Fix Kconfig dependencies mtd: rawnand: sunxi: #undef field_{get,prep}() before local definition mailmap: update Pratyush Yadav's email address mtd: spi-nor: core: Check read CR support mtd: spi-nor: micron-st: add TODO for fixing mt35xu02gcba mtd: spi-nor: micron-st: add mt35xu01gbba support mtd: spi-nor: micron-st: use SFDP of mt35xu512aba mtd: spi-nor: micron-st: move set_octal_dtr to late_init() mtd: spi-nor: micron-st: rename the die_late_init functions mtd: spinand: esmt: add support for F50L1G41LC mtd: rawnand: lpc32xx_slc: Convert to use devm_gpiod_get_optional() mtd: mtdpart: ignore error -ENOENT from parsers on subpartitions mtd: maps: pcmciamtd: fix potential memory leak in pcmciamtd_detach() mtd: spi-nor: spansion: SMPT fixups for S25FS-S ...

mtd: rawnand: renesas: Handle devm_pm_runtime_enable() errors

2025-11-28T08:11:59Z

devm_pm_runtime_enable() can fail due to memory allocation failures. The current code ignores its return value and proceeds with pm_runtime_resume_and_get(), which may operate on incorrectly initialized runtime PM state. Check the return value of devm_pm_runtime_enable() and return the error code if it fails. Fixes: 6a2277a0ebe7 ("mtd: rawnand: renesas: Use runtime PM instead of the raw clock API") Signed-off-by: Haotian Zhang Reviewed-by: Geert Uytterhoeven Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: #undef field_{get,prep}() before local definition

2025-11-27T17:24:01Z

Prepare for the advent of globally available common field_get() and field_prep() macros by undefining the symbols before defining local variants. This prevents redefinition warnings from the C preprocessor when introducing the common macros later. Suggested-by: Yury Norov Signed-off-by: Geert Uytterhoeven

mtd: rawnand: lpc32xx_slc: Convert to use devm_gpiod_get_optional()

2025-11-17T10:52:17Z

The initial fix for a GPIO descriptor leak added manual gpiod_put() calls in the error path and remove function. This follow-up patch improves upon the fix by switching to the resource-managed devm_gpiod_get_optional() API. Suggested-by: Vladimir Zapolskiy Signed-off-by: Haotian Zhang Reviewed-by: Vladimir Zapolskiy Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: Add support for H616 nand controller

2025-10-28T16:18:13Z

The H616 nand controller has the same base as A10/A23, with some differences: - mdma is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. Introduce the basic support, with ECC and scrambling, but without DMA/MDMA. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: introduce sram_size in sunxi_nfc_caps

2025-10-28T16:18:13Z

The H6/H616 the SRAM is bigger than the A10/A23 one, so move its size into sunxi_nfc_caps. No functional change Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: introduce ecc_err_mask in sunxi_nfc_caps

2025-10-28T16:18:13Z

The H6/H616 error mask register is bigger than the A10/A23 one, so move its mask into sunxi_nfc_caps. No functional change Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal