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<title>kernel/drivers/mtd/nand/core.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
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<updated>2025-09-18T08:32:00Z</updated>
<entry>
<title>mtd: nand: move nand_check_erased_ecc_chunk() to nand/core</title>
<updated>2025-09-18T08:32:00Z</updated>
<author>
<name>Markus Stockhausen</name>
<email>markus.stockhausen@gmx.de</email>
</author>
<published>2025-09-10T18:32:58Z</published>
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<id>urn:sha1:6b88293aae7fb78872e5cc1ec36e2f750ae12e38</id>
<content type='text'>
The check function for bitflips in erased blocks will be needed
by the Realtek ECC engine driver (which is currently under
development). Right now it is located in raw/nand_base.c.
While this is sufficient for the current usecases, there is
no real dependency for an ECC engine on the raw nand library.

Move the function over to a more generic place in core library.

Suggested-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase()</title>
<updated>2022-11-07T16:17:20Z</updated>
<author>
<name>Dario Binacchi</name>
<email>dario.binacchi@amarulasolutions.com</email>
</author>
<published>2022-10-18T17:02:05Z</published>
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<id>urn:sha1:a50ae8c98e5766a4fcb78e76f13cc658b784eac1</id>
<content type='text'>
This function is only used within this module, so it is no longer
necessary to use EXPORT_SYMBOL_GPL().

Signed-off-by: Dario Binacchi &lt;dario.binacchi@amarulasolutions.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com
</content>
</entry>
<entry>
<title>Merge tag 'mtd/spi-mem-ecc-for-5.18' into mtd/next</title>
<updated>2022-02-18T14:11:12Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2022-02-18T14:11:12Z</published>
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<id>urn:sha1:d71dac3b897f51d7d1fcf28d2a2ab29e541a6cda</id>
<content type='text'>
Topic branch bringing-in changes related to the support of ECC engines
that can be used by SPI controllers to manage SPI NANDs as well as
possibly by parallel NAND controllers. In particular, it brings support
for Macronix ECC engine that can be used with Macronix SPI controller.

The changes touch the NAND core, the NAND ECC core, the spi-mem layer, a
SPI controller driver and add a new NAND ECC driver, as well as a number
of binding updates.

Binding changes:
* Vendor prefixes: Clarify Macronix prefix
* SPI NAND: Convert spi-nand description file to yaml
* Raw NAND chip: Create a NAND chip description
* Raw NAND controller:
  - Harmonize the property types
  - Fix a comment in the examples
  - Fix the reg property description
* Describe Macronix NAND ECC engine
* Macronix SPI controller:
  - Document the nand-ecc-engine property
  - Convert to yaml
  - The interrupt property is not mandatory

NAND core changes:
* ECC:
  - Add infrastructure to support hardware engines
  - Add a new helper to retrieve the ECC context
  - Provide a helper to retrieve a pilelined engine device

NAND-ECC changes:
* Macronix ECC engine:
  - Add Macronix external ECC engine support
  - Support SPI pipelined mode

SPI-NAND core changes:
* Delay a little bit the dirmap creation
* Create direct mapping descriptors for ECC operations

SPI-NAND driver changes:
* macronix: Use random program load

SPI changes:
* Macronix SPI controller:
  - Fix the transmit path
  - Create a helper to configure the controller before an operation
  - Create a helper to ease the start of an operation
  - Add support for direct mapping
  - Add support for pipelined ECC operations
* spi-mem:
  - Introduce a capability structure
  - Check the controller extra capabilities
  - cadence-quadspi/mxic: Provide capability structures
  - Kill the spi_mem_dtr_supports_op() helper
  - Add an ecc parameter to the spi_mem_op structure
</content>
</entry>
<entry>
<title>mtd: Replace the expert mode symbols with a single helper</title>
<updated>2022-02-07T15:36:11Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2022-01-28T11:34:14Z</published>
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<id>urn:sha1:ad5e35f58384179bbd3cdb349904e150f364c4f3</id>
<content type='text'>
Reduce the number of exported symbols by replacing:
- mtd_expert_analysis_warning (the error string)
- mtd_expert_analysis_mode (the boolean)
with a single helper:
- mtd_check_expert_analysis_mode

Calling this helper will both check/return the content of the internal
boolean -which is not exported anymore- and as well conditionally
WARN_ONCE() the user, like it was done before.

While on this function, make the error string local to the helper and
set it const. Only export this helper when CONFIG_DEBUG_FS is defined to
limit the growth of the Linux kernel size only for a debug feature on
production kernels.

Mechanically update all the consumers.

Suggested-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20220128113414.1121924-1-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: nand: ecc: Add infrastructure to support hardware engines</title>
<updated>2022-01-23T11:36:23Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2021-12-16T11:16:38Z</published>
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<id>urn:sha1:96489c1c0b53131b0e1ec33e2060538379ad6152</id>
<content type='text'>
Add the necessary helpers to register/unregister hardware ECC engines
that will be called from ECC engine drivers.

Also add helpers to get the right engine from the user
perspective. Keep a reference of the in use ECC engine in order to
prevent modules to be unloaded. Put the reference when the engine gets
retired.

A static list of hardware (only) ECC engines is setup to keep track of
the registered engines.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: Introduce an expert mode for forensics and debugging purposes</title>
<updated>2021-12-09T16:51:59Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2021-11-18T11:46:59Z</published>
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<id>urn:sha1:67b967ddd93d0ed57d392a00f6f90060f0910c0e</id>
<content type='text'>
When developping NAND controller drivers or when debugging filesystem
corruptions, it is quite common to need hacking locally into the
MTD/NAND core in order to get access to the content of the bad
blocks. Instead of having multiple implementations out there let's
provide a simple yet effective specific MTD-wide debugfs entry to fully
disable these checks on purpose.

A warning is added to inform the user when this mode gets enabled.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20211118114659.1282855-1-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: nand: Add helpers to manage ECC engines and configurations</title>
<updated>2020-12-10T21:37:30Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2020-10-01T10:20:09Z</published>
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<id>urn:sha1:6b0c3b84156125e029956e46d2b44e72f513a9fa</id>
<content type='text'>
Add the logic in the NAND core to find the right ECC engine depending
on the NAND chip requirements and the user desires. Right now, the
choice may be made between (more will come):
* software Hamming
* software BCH
* on-die (SPI-NAND devices only)

Once the ECC engine has been found, the ECC engine must be
configured.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20201001102014.20100-2-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg</title>
<updated>2019-04-08T08:21:08Z</updated>
<author>
<name>Boris Brezillon</name>
<email>bbrezillon@kernel.org</email>
</author>
<published>2018-11-04T13:43:37Z</published>
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<id>urn:sha1:377e517b5fa53590418a7b4c2206082d92434fa3</id>
<content type='text'>
NAND datasheets usually give the maximum number of bad blocks per LUN
and this number can be used to help upper layers decide how much blocks
they should reserve for bad block handling.

Add a max_bad_eraseblocks_per_lun to the nand_memory_organization
struct and update the NAND_MEMORG() macro (and its users) accordingly.

We also provide a default mtd-&gt;_max_bad_blocks() implementation.

Signed-off-by: Boris Brezillon &lt;bbrezillon@kernel.org&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Reviewed-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
</content>
</entry>
<entry>
<title>mtd: nand: Fix nanddev_mtd_erase()</title>
<updated>2018-04-22T17:59:29Z</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@bootlin.com</email>
</author>
<published>2018-04-10T15:15:13Z</published>
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<id>urn:sha1:23566c3798f315058862564ab3d01882316054eb</id>
<content type='text'>
Commit e7bfb3fdbde3 ("mtd: Stop updating erase_info-&gt;state and calling
mtd_erase_callback()") removed the einfo-&gt;state field and the
MTD_ERASE_XXX macros. At the same time, the generic NAND layer was added
and made sure to update the erase info state.

It did not result in a build failure after merging the nand/for-4.17
branch in mtd/next because the generic NAND layer is not selected yet.
Let's fix that before a config option starts selecting MTD_NAND_CORE.

Fixes: e7bfb3fdbde3 ("mtd: Stop updating erase_info-&gt;state and calling mtd_erase_callback()")
Signed-off-by: Boris Brezillon &lt;boris.brezillon@bootlin.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: Fix some function description mismatches in core.c</title>
<updated>2018-03-29T17:41:57Z</updated>
<author>
<name>Xiaolei Li</name>
<email>xiaolei.li@mediatek.com</email>
</author>
<published>2018-03-29T01:34:59Z</published>
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<id>urn:sha1:097ccca726ffedb277c104aba45c59d075969e51</id>
<content type='text'>
In core.c, some function descriptions do not match function
definitions. Just fix these mismatches.

Signed-off-by: Xiaolei Li &lt;xiaolei.li@mediatek.com&gt;
Signed-off-by: Boris Brezillon &lt;boris.brezillon@bootlin.com&gt;
</content>
</entry>
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