<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/memory, branch linux-4.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.2.y</id>
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<updated>2015-09-29T17:33:33Z</updated>
<entry>
<title>iommu/tegra-smmu: Parameterize number of TLB lines</title>
<updated>2015-09-29T17:33:33Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-08-06T12:20:31Z</published>
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<id>urn:sha1:218014334367fca6910477b2430dfa6680eebdf7</id>
<content type='text'>
commit 11cec15bf3fb498206ef63b1fa26c27689e02d0e upstream.

The number of TLB lines was increased from 16 on Tegra30 to 32 on
Tegra114 and later. Parameterize the value so that the initial default
can be set accordingly.

On Tegra30, initializing the value to 32 would effectively disable the
TLB and hence cause massive latencies for memory accesses translated
through the SMMU. This is especially noticeable for isochronuous clients
such as display, whose FIFOs would continuously underrun.

Fixes: 891846516317 ("memory: Add NVIDIA Tegra memory controller support")
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>memory: omap-gpmc: Don't try to save uninitialized GPMC context</title>
<updated>2015-08-12T08:43:49Z</updated>
<author>
<name>Tomeu Vizoso</name>
<email>tomeu.vizoso@collabora.com</email>
</author>
<published>2015-08-05T12:24:15Z</published>
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<id>urn:sha1:e984a1791ac6a7c944911207e8a9c344763f0003</id>
<content type='text'>
If for some reason the GPMC device hasn't been probed yet, gpmc_base is
going to be NULL. Because there's no context yet to be saved, just turn
these functions into no-ops until that device gets probed.

Unable to handle kernel NULL pointer dereference at virtual address 00000010
pgd = c0204000
[00000010] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.2.0-rc5-next-20150804-05947-g23f38fe8eda9 #1
Hardware name: Generic OMAP3-GP (Flattened Device Tree)
task: c0e623e8 ti: c0e5c000 task.ti: c0e5c000
PC is at omap3_gpmc_save_context+0x8/0xc4
LR is at omap_sram_idle+0x154/0x23c
pc : [&lt;c087c7ac&gt;]    lr : [&lt;c023262c&gt;]    psr: 60000193
sp : c0e5df40  ip : c0f92a80  fp : c0999eb0
r10: c0e57364  r9 : c0e66f14  r8 : 00000003
r7 : 00000000  r6 : 00000003  r5 : 00000000  r4 : c0f5f174
r3 : c0fa4fe8  r2 : 00000000  r1 : 00000000  r0 : fa200280
Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 80204019  DAC: 00000015
Process swapper/0 (pid: 0, stack limit = 0xc0e5c220)
Stack: (0xc0e5df40 to 0xc0e5e000)
df40: 00000000 c0e66ef8 c0f5f1a4 00000000 00000003 c02333a4 c3813822 00000000
df60: 00000000 c0e5a5c8 cfb8a5d0 c07f0c44 0e4f1d7e 00000000 00000000 00000000
df80: c3813822 00000000 cfb8a5d0 c0e5e4e4 cfb8a5d0 c0e66f14 c0e5a5c8 c0e5e54c
dfa0: c0e5e544 c0e57364 c0999eb0 c0277758 000000fa c0f5d000 00000000 c0d61c18
dfc0: ffffffff ffffffff 00000000 c0d61674 00000000 c0df7a48 00000000 c0f5d5d4
dfe0: c0e5e4c0 c0df7a44 c0e634f8 80204059 00000000 8020807c 00000000 00000000
[&lt;c087c7ac&gt;] (omap3_gpmc_save_context) from [&lt;c023262c&gt;] (omap_sram_idle+0x154/0x23c)
[&lt;c023262c&gt;] (omap_sram_idle) from [&lt;c02333a4&gt;] (omap3_enter_idle_bm+0xec/0x1a8)
[&lt;c02333a4&gt;] (omap3_enter_idle_bm) from [&lt;c07f0c44&gt;] (cpuidle_enter_state+0xbc/0x284)
[&lt;c07f0c44&gt;] (cpuidle_enter_state) from [&lt;c0277758&gt;] (cpu_startup_entry+0x174/0x24c)
[&lt;c0277758&gt;] (cpu_startup_entry) from [&lt;c0d61c18&gt;] (start_kernel+0x358/0x3c0)
[&lt;c0d61c18&gt;] (start_kernel) from [&lt;8020807c&gt;] (0x8020807c)
Code: c0ccace8 c0ccacc0 e59f30b4 e5932000 (e5921010)

Signed-off-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
Suggested-by: Javier Martinez Canillas &lt;javier@dowhile0.org&gt;
Reviewed-by: Javier Martinez Canillas &lt;javier@osg.samsung.com&gt;
Acked-by: Roger Quadros &lt;rogerq@ti.com&gt;
[tony@atomide.com: updated description as suggested by Javier]
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'fixes-rc1' into omap-for-v4.2/fixes</title>
<updated>2015-07-06T12:33:17Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2015-07-06T12:33:17Z</published>
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<id>urn:sha1:ae745302c0a3e2b5b768690f631fc14db44467e7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2015-06-26T18:54:29Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-06-26T18:54:29Z</published>
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<id>urn:sha1:f5dcb68086ba2e033b2af32b0da0c7a7c7872a09</id>
<content type='text'>
Pull ARM SoC driver updates from Kevin Hilman:
 "Some of these are for drivers/soc, where we're now putting
  SoC-specific drivers these days.  Some are for other driver subsystems
  where we have received acks from the appropriate maintainers.

  Some highlights:

   - simple-mfd: document DT bindings and misc updates
   - migrate mach-berlin to simple-mfd for clock, pinctrl and reset
   - memory: support for Tegra132 SoC
   - memory: introduce tegra EMC driver for scaling memory frequency
   - misc. updates for ARM CCI and CCN busses"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  drivers: soc: sunxi: Introduce SoC driver to map SRAMs
  arm-cci: Add aliases for PMU events
  arm-cci: Add CCI-500 PMU support
  arm-cci: Sanitise CCI400 PMU driver specific code
  arm-cci: Abstract handling for CCI events
  arm-cci: Abstract out the PMU counter details
  arm-cci: Cleanup PMU driver code
  arm-cci: Do not enable CCI-400 PMU by default
  firmware: qcom: scm: Add HDCP Support
  ARM: berlin: add an ADC node for the BG2Q
  ARM: berlin: remove useless chip and system ctrl compatibles
  clk: berlin: drop direct of_iomap of nodes reg property
  ARM: berlin: move BG2Q clock node
  ARM: berlin: move BG2CD clock node
  ARM: berlin: move BG2 clock node
  clk: berlin: prepare simple-mfd conversion
  pinctrl: berlin: drop SoC stub provided regmap
  ARM: berlin: move pinctrl to simple-mfd nodes
  pinctrl: berlin: prepare to use regmap provided by syscon
  reset: berlin: drop arch_initcall initialization
  ...
</content>
</entry>
<entry>
<title>memory: omap-gpmc: Add Kconfig option for debug</title>
<updated>2015-06-02T01:22:10Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2015-06-02T01:22:10Z</published>
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<id>urn:sha1:63aa945b1013c34b145dcf218d4ea323cbd93f86</id>
<content type='text'>
We support decoding the bootloader values if DEBUG is defined.
But we also need to change the struct omap_hwmod flags to have
HWMOD_INIT_NO_RESET to avoid the GPMC being reset during the
boot. Otherwise just the default timings will be displayed
instead of the bootloader configured timings.

This also allows us to clean up the various GPMC related
hwmod flags. For debugging, we only need HWMOD_INIT_NO_RESET,
and HWMOD_INIT_NO_IDLE is not needed.

Cc: Brian Hutchinson &lt;b.hutchman@gmail.com&gt;
Cc: Paul Walmsley &lt;paul@pwsan.com&gt;
Cc: Roger Quadros &lt;rogerq@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;
</content>
</entry>
<entry>
<title>memory: omap-gpmc: Fix parsing of devices</title>
<updated>2015-06-01T22:00:44Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2015-06-01T22:00:44Z</published>
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<id>urn:sha1:28a7eedd1109c9277390f44aa11de76b673996cd</id>
<content type='text'>
We currently artificially limit the parsing of GPMC connected
devices based on the device name. Let's stop doing that, it's
confusing as adding devices to .dts files with using normal
names like fpga and usb will currently cause them to not probe.

Cc: Roger Quadros &lt;rogerq@ti.com&gt;
Reported-by: Brian Hutchinson &lt;b.hutchman@gmail.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers</title>
<updated>2015-05-13T15:59:35Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2015-05-13T15:59:35Z</published>
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<id>urn:sha1:44fb3026ad28d2a2b935dc9c47ec2dffadca3f35</id>
<content type='text'>
Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding:

This introduces the EMC driver that's required to scale the external
memory frequency.

* tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  memory: tegra: Add EMC frequency debugfs entry
  memory: tegra: Add EMC (external memory controller) driver
  memory: tegra: Add API needed by the EMC driver
  of: Add Tegra124 EMC bindings
  of: Document timings subnode of nvidia,tegra-mc
</content>
</entry>
<entry>
<title>memory: tegra: Add EMC frequency debugfs entry</title>
<updated>2015-05-05T09:39:48Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2015-03-12T14:48:06Z</published>
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<id>urn:sha1:9c77a81f215bfeee8f96c50c8ab27dbebffec80d</id>
<content type='text'>
This file in debugfs can be used to get or set the EMC frequency.
Reading the file will return the currently set frequency in Hz, while
writing the file sets the specified frequency rounded to the next
highest frequency supported by the board.

Will be very useful when tuning memory scaling.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
[treding@nvidia.com: add "emc" debugfs directory]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add EMC (external memory controller) driver</title>
<updated>2015-05-05T09:12:17Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2015-03-12T14:48:03Z</published>
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<id>urn:sha1:73a7f0a90641b09300d47308682b674c570dd6a2</id>
<content type='text'>
Implements functionality needed to change the rate of the memory bus
clock.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add API needed by the EMC driver</title>
<updated>2015-05-05T09:10:19Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2015-03-12T14:48:02Z</published>
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<id>urn:sha1:3d9dd6fdd23695a038633f1a87aee0708fe4b8e0</id>
<content type='text'>
The EMC driver needs to know the number of external memory devices and
also needs to update the EMEM configuration based on the new rate of the
memory bus.

To know how to update the EMEM config, looks up the values of the burst
regs in the DT, for a given timing.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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