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<title>kernel/drivers/memory/tegra30-mc.c, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2014-12-04T15:11:47Z</updated>
<entry>
<title>memory: Add NVIDIA Tegra memory controller support</title>
<updated>2014-12-04T15:11:47Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-04-16T07:24:44Z</published>
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<id>urn:sha1:8918465163171322c77a19d5258a95f56d89d2e4</id>
<content type='text'>
The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.

Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
custom API or a generic subsystem) to allow clients to register latency
requirements.

This driver also registers an IOMMU (SMMU) that's implemented by the
memory controller. It is supported on Tegra30, Tegra114 and Tegra124
currently. Tegra20 has a GART instead.

The Tegra SMMU operates on memory clients and SWGROUPs. A memory client
is a unidirectional, special-purpose DMA master. A SWGROUP represents a
set of memory clients that form a logical functional unit corresponding
to a single device. Typically a device has two clients: one client for
read transactions and one client for write transactions, but there are
also devices that have only read clients, but many of them (such as the
display controllers).

Because there is no 1:1 relationship between memory clients and devices
the driver keeps a table of memory clients and the SWGROUPs that they
belong to per SoC. Note that this is an exception and due to the fact
that the SMMU is tightly integrated with the rest of the Tegra SoC. The
use of these tables is discouraged in drivers for generic IOMMU devices
such as the ARM SMMU because the same IOMMU could be used in any number
of SoCs and keeping such tables for each SoC would not scale.

Acked-by: Joerg Roedel &lt;jroedel@suse.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: simplify use of devm_ioremap_resource</title>
<updated>2013-08-15T22:04:42Z</updated>
<author>
<name>Julia Lawall</name>
<email>Julia.Lawall@lip6.fr</email>
</author>
<published>2013-08-14T09:11:10Z</published>
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<id>urn:sha1:946a88df76a2c5a9f4087fb41efd9d2763872302</id>
<content type='text'>
Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// &lt;smpl&gt;
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
// &lt;/smpl&gt;

Signed-off-by: Julia Lawall &lt;Julia.Lawall@lip6.fr&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra30-mc: Fix IRQ handler.</title>
<updated>2013-06-17T23:46:06Z</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>ttynkkynen@nvidia.com</email>
</author>
<published>2013-06-11T10:11:19Z</published>
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<id>urn:sha1:36dd68319c7b56a76ed450b0e470067b5d74b9b2</id>
<content type='text'>
In Tegra30 any memory controller interrupt would cause an infinite loop in the
IRQ handler. Additionally, a garbage pointer was used to read the MC
status registers, which causes wrong values to be printed if a MC error
occurred.

Signed-off-by: Tuomas Tynkkynen &lt;ttynkkynen@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra30: Fix build error w/o PM</title>
<updated>2013-03-15T18:10:49Z</updated>
<author>
<name>Hiroshi Doyu</name>
<email>hdoyu@nvidia.com</email>
</author>
<published>2013-03-14T09:12:10Z</published>
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<id>urn:sha1:9f7345b7a7cbf4c78a8161cba21de1772d5ad56e</id>
<content type='text'>
Make this depend on CONFIG_PM.

Signed-off-by: Hiroshi Doyu &lt;hdoyu@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>memory: Convert to devm_ioremap_resource()</title>
<updated>2013-01-22T19:41:56Z</updated>
<author>
<name>Thierry Reding</name>
<email>thierry.reding@avionic-design.de</email>
</author>
<published>2013-01-21T10:09:08Z</published>
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<id>urn:sha1:06303c2e00701724acb95069ca46f87c998c4be1</id>
<content type='text'>
Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.

devm_ioremap_resource() provides its own error messages so all explicit
error messages can be removed from the failure code paths.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Drivers: memory: remove __dev* attributes.</title>
<updated>2013-01-03T23:57:14Z</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2012-12-21T23:06:41Z</published>
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<id>urn:sha1:27796aa0dce01661fedb5f3fa6b11db13f02a77f</id>
<content type='text'>
CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, and
__devinitconst, from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton &lt;wfp5p@virginia.edu&gt;
Cc: Hiroshi DOYU &lt;hdoyu@nvidia.com&gt;
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Axel Lin &lt;axel.lin@gmail.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra{20,30}-mc: Fix reading incorrect register in mc_readl()</title>
<updated>2012-09-26T21:04:09Z</updated>
<author>
<name>Axel Lin</name>
<email>axel.lin@gmail.com</email>
</author>
<published>2012-09-20T01:32:53Z</published>
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<id>urn:sha1:e0f21e6d52cc245e7d4f7e02ca4b7b6571660ec2</id>
<content type='text'>
The code reading the register does not match the code writing to the register,
fix it.

Also fix the coding style in mc_writel() for better readability.

Signed-off-by: Axel Lin &lt;axel.lin@gmail.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra{20,30}-mc: Remove empty *_remove()</title>
<updated>2012-05-14T19:52:52Z</updated>
<author>
<name>Hiroshi DOYU</name>
<email>hdoyu@nvidia.com</email>
</author>
<published>2012-05-14T16:20:03Z</published>
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<id>urn:sha1:7458eab6f4527bce719703eb15fef1cff9e8d9e0</id>
<content type='text'>
Remove unnecessary empty functions.

Signed-off-by: Hiroshi DOYU &lt;hdoyu@nvidia.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra{20,30}-mc: Use dev_err_ratelimited()</title>
<updated>2012-05-14T15:47:11Z</updated>
<author>
<name>Hiroshi DOYU</name>
<email>hdoyu@nvidia.com</email>
</author>
<published>2012-05-14T10:07:03Z</published>
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<id>urn:sha1:90394482b807cb0a474fb387ed020603df14cfd0</id>
<content type='text'>
Introduce a new dev_*_ratelimited() instead of pr_*_ratelimited() for
better info to print.

Signed-off-by: Hiroshi DOYU &lt;hdoyu@nvidia.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>ARM: tegra30: MC: Remove unnecessary BUG*()</title>
<updated>2012-05-11T22:21:27Z</updated>
<author>
<name>Hiroshi DOYU</name>
<email>hdoyu@nvidia.com</email>
</author>
<published>2012-05-11T10:04:45Z</published>
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<id>urn:sha1:b37fd4154e758c7226fda663e2ea3a97c6e8c732</id>
<content type='text'>
Accessing interleaved MC register offsets/ranges are verified. BUG*()s
in accessors can be removed.

Signed-off-by: Hiroshi DOYU &lt;hdoyu@nvidia.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
