<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/memory/tegra/tegra114.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y'/>
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<updated>2021-06-03T19:49:41Z</updated>
<entry>
<title>memory: tegra: Extract setup code into callback</title>
<updated>2021-06-03T19:49:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-02T16:32:56Z</published>
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<id>urn:sha1:ddeceab0a959d199de776eaf5da977574b7c8f16</id>
<content type='text'>
Separate the setup code for Tegra30 and later into a -&gt;setup() callback
and set it for all applicable chips.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210602163302.120041-7-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Consolidate register fields</title>
<updated>2021-06-03T19:49:40Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-02T16:32:51Z</published>
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<id>urn:sha1:4f1ac76e5ed9436ff3cd72e308527fd1e90b193a</id>
<content type='text'>
Subsequent patches will add more register fields to the tegra_mc_client
structure, so consolidate all register field definitions into a common
sub-structure for coherency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add missing latency allowness entry for Page Table Cache</title>
<updated>2020-11-26T17:50:35Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-04T16:49:07Z</published>
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<id>urn:sha1:d5ecac0afa30811901eb401067f196e688aeb73e</id>
<content type='text'>
Add missing PTC memory client latency allowness entry to the Tegra MC
drivers.

This prevents erroneous clearing of MC_INTSTATUS 0x0 register during
of the LA programming in tegra_mc_setup_latency_allowance() due to the
missing entry. Note that this patch doesn't fix any known problems.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201104164923.21238-32-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add gr2d and gr3d to DRM IOMMU group</title>
<updated>2019-11-11T13:55:25Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-10-28T12:37:07Z</published>
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<id>urn:sha1:63a613fdb16cc2efba7222b1eb8cee0aba070fb2</id>
<content type='text'>
All of the devices making up the Tegra DRM device want to share a single
IOMMU domain. Put them into a single group to allow them to do that.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500</title>
<updated>2019-06-19T15:09:55Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-06-04T08:11:33Z</published>
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<id>urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520</id>
<content type='text'>
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Fix a typos for "fdcdwr2" mc client</title>
<updated>2019-04-18T09:51:17Z</updated>
<author>
<name>Edward Cragg</name>
<email>drq.11235@gmail.com</email>
</author>
<published>2019-03-08T11:21:55Z</published>
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<id>urn:sha1:67a8d5b0fadfd931f7e6a78e9ee7b2792a7114aa</id>
<content type='text'>
Fix typo for fdcwr2 to fdcdwr2 to match the TRM.

Signed-off-by: Edward Cragg &lt;drq.11235@gmail.com&gt;
Signed-off-by: Kejia Hu &lt;kejia.hu@codethink.co.uk&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Properly spell "tegra"</title>
<updated>2019-04-11T15:58:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-04-11T08:48:25Z</published>
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<id>urn:sha1:cb2b58391e40d0877b1f60023c8be72696ff8511</id>
<content type='text'>
Rename all occurrences of "terga" to "tegra". It's an easy typo to make
and a difficult one to spot.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Remove Tegra114 SATA and AFI reset definitions</title>
<updated>2018-05-18T20:45:01Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-05-08T16:49:47Z</published>
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<id>urn:sha1:5fd80cf74e1ee06f9895b74d26a3efb01bdad033</id>
<content type='text'>
Tegra114 doesn't have SATA nor PCIe, but TRM seems erroneously document
them.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add Tegra114 memory controller hot resets</title>
<updated>2018-04-30T08:12:21Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-04-13T11:33:52Z</published>
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<id>urn:sha1:3788c4ed4a38cb9329ac202fa1b77f738c1ae0a4</id>
<content type='text'>
Define the table of memory controller hot resets for Tegra114.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Apply interrupts mask per SoC</title>
<updated>2018-04-27T09:23:04Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-04-09T19:28:29Z</published>
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<id>urn:sha1:1c74d5c0de0c2cc29fef97a19251da2ad6f579bd</id>
<content type='text'>
Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
