Hosts the 0x221E linux distro kernel. https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-3.11.y 2013-11-29T18:42:15Z 2013-11-29T18:42:15Z Peter Zijlstra peterz@infradead.org 2013-09-11T10:43:13Z urn:sha1:f484c09fbbdf2c97175ab7f08ab713e5d88ff99f commit ea8117478918a4734586d35ff530721b682425be upstream. Mike reported that commit 7d1a9417 ("x86: Use generic idle loop") regressed several workloads and caused excessive reschedule interrupts. The patch in question failed to notice that the x86 code had an inverted sense of the polling state versus the new generic code (x86: default polling, generic: default !polling). Fix the two prominent x86 mwait based idle drivers and introduce a few new generic polling helpers (fixing the wrong smp_mb__after_clear_bit usage). Also switch the idle routines to using tif_need_resched() which is an immediate TIF_NEED_RESCHED test as opposed to need_resched which will end up being slightly different. Reported-by: Mike Galbraith <bitbucket@online.de> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: lenb@kernel.org Cc: tglx@linutronix.de Link: http://lkml.kernel.org/n/tip-nc03imb0etuefmzybzj7sprf@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2013-05-11T22:23:17Z Linus Torvalds torvalds@linux-foundation.org 2013-05-11T22:23:17Z urn:sha1:ac4e01093f6d7b051c5d6a3e61ea5337774ac36a Pull idle update from Len Brown: "Add support for new Haswell-ULT CPU idle power states" * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux: intel_idle: initial C8, C9, C10 support tools/power turbostat: display C8, C9, C10 residency 2013-04-27T23:54:49Z Rafael J. Wysocki rafael.j.wysocki@intel.com 2013-04-27T23:54:49Z urn:sha1:e4f5a3adc454745fea35f1c312e14cbeba6e0ea4 * pm-cpuidle: (51 commits) cpuidle: add maintainer entry ARM: s3c64xx: cpuidle: use init/exit common routine SH: cpuidle: use init/exit common routine cpuidle: fix comment format ARM: imx: cpuidle: use init/exit common routine ARM: davinci: cpuidle: use init/exit common routine ARM: kirkwood: cpuidle: use init/exit common routine ARM: calxeda: cpuidle: use init/exit common routine ARM: tegra: cpuidle: use init/exit common routine for tegra3 ARM: tegra: cpuidle: use init/exit common routine for tegra2 ARM: OMAP4: cpuidle: use init/exit common routine ARM: shmobile: cpuidle: use init/exit common routine ARM: tegra: cpuidle: use init/exit common routine ARM: OMAP3: cpuidle: use init/exit common routine ARM: at91: cpuidle: use init/exit common routine ARM: ux500: cpuidle: use init/exit common routine cpuidle: make a single register function for all ARM: ux500: cpuidle: replace for_each_online_cpu by for_each_possible_cpu cpuidle: remove en_core_tk_irqen flag ARM: OMAP3: remove cpuidle_wrap_enter ... 2013-04-23T11:45:22Z Daniel Lezcano daniel.lezcano@linaro.org 2013-04-23T08:54:31Z urn:sha1:554c06ba3ee29cf453fca17e9e61120b75aa476d The en_core_tk_irqen flag is set in all the cpuidle driver which means it is not necessary to specify this flag. Remove the flag and the code related to it. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Kevin Hilman <khilman@linaro.org> # for mach-omap2/* Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 2013-04-21T22:21:29Z Daniel Lezcano daniel.lezcano@linaro.org 2013-04-21T22:21:29Z urn:sha1:94b4624986071a875871378f2a84e3f816764372 The start/stop_critical_timings are called from arch/x86/kernel/process.c in the cpu_idle loop function. Remove the ones in the cpuidle driver. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 2013-04-17T23:23:32Z Len Brown len.brown@intel.com 2013-02-27T18:18:50Z urn:sha1:86239ceb33b0d8480b0f0ca0eec08e7f7a807374 Allow intel_idle and cpuidle to utilize C8, C9, C10 when they are present on... "Fourth Generation Intel(R) Core(TM) Processors", which are based on Intel(R) microarchitecture code name Haswell. Signed-off-by: Len Brown <len.brown@intel.com> 2013-03-15T14:55:31Z Len Brown len.brown@intel.com 2013-03-15T14:55:31Z urn:sha1:0b15841b0bbbde75134a777c543dc51fe6187108 There is an additional HSW CPU-id, 0x46, which has C-states exactly like CPU-id 0x45. Signed-off-by: Len Brown <len.brown@intel.com> 2013-02-13T23:22:08Z Len Brown len.brown@intel.com 2013-02-02T06:31:56Z urn:sha1:32e9518005c8dd9ed668f40f98632c8186df4909 Here we disable HW promotion of C1 to C1E and export both C1 and C1E and distinct C-states. This allows a cpuidle governor to choose a lower latency C-state than C1E when necessary to satisfy performance and QOS constraints -- and still save power versus polling. This also corrects the erroneous latency previously reported for C1E -- it is 10usec, not 1usec. Note that if you use "intel_idle.max_cstate=N", then you must increment N by 1 to get the same behavior after this change. Signed-off-by: Len Brown <len.brown@intel.com> 2013-02-09T00:29:16Z Len Brown len.brown@intel.com 2013-02-02T04:37:30Z urn:sha1:e022e7eb90f3edb83f9ff77825eda3d1b3a2f2e0 Remove the assumption that cstate_tables are indexed by MWAIT flag values. Each entry identifies itself via its own flags value. This change is needed to support multiple states that share the same MWAIT flags. Note that this can have an effect on what state is described by 'N' on cmdline intel_idle.max_cstate=N on some systems. intel_idle.max_cstate=0 still disables the driver intel_idle.max_cstate=1 still results in just C1(E) However, "place holders" in the sparse C-state name-space (eg. Atom) have been removed. Signed-off-by: Len Brown <len.brown@intel.com> 2013-02-09T00:28:10Z Len Brown len.brown@intel.com 2013-02-02T02:35:35Z urn:sha1:137ecc779c80138723677209730738d76262e810 Cosmetic only. Replace use of MWAIT_MAX_NUM_CSTATES with CPUIDLE_STATE_MAX. They are both 8, so this patch has no functional change. The reason to change is that intel_idle will soon be able to export more than the 8 "major" states supported by MWAIT. When we hit that limit, it is important to know where the limit comes from. Signed-off-by: Len Brown <len.brown@intel.com>