kernel/drivers/hwmon/occ, branch linux-5.1.y

hwmon: (occ) Fix extended status bits

2019-05-16T17:35:33Z

commit b88c5049219a7f322bb1fd65fc30d17472a23563 upstream. The occ's extended status is checked and shown as sysfs attributes. But the code was incorrectly checking the "status" bits. Fix it by checking the "ext_status" bits. Cc: stable@vger.kernel.org Fixes: df04ced684d4 ("hwmon (occ): Add sysfs attributes for additional OCC data") Signed-off-by: Lei YU Reviewed-by: Eddie James Signed-off-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman

hwmon: (occ) Fix power sensor indexing

2019-03-29T16:51:44Z

In the case of power sensor version 0xA0, the sensor indexing overlapped with the "caps" power sensors, resulting in probe failure and kernel warnings. Fix this by specifying the next index for each power sensor version. Fixes: 54076cb3b5ff ("hwmon (occ): Add sensor attributes and register ...") Cc: stable@vger.kernel.org Signed-off-by: Eddie James Tested-by: Joel Stanley Signed-off-by: Guenter Roeck

hwmon: (occ) Fix license headers

2019-02-18T22:23:29Z

Files have inconsistent license information. Signed-off-by: Eddie James Signed-off-by: Guenter Roeck

hwmon: (occ) Fix potential integer overflow

2019-01-08T05:03:59Z

Cast get_unaligned_be32(...) to u64 in order to give the compiler complete information about the proper arithmetic to use and avoid a potential integer overflow. Notice that such function call is used in contexts that expect expressions of type u64 (64 bits, unsigned); and the following expressions are currently being evaluated using 32-bit arithmetic: val = get_unaligned_be32(&power->update_tag) * occ->powr_sample_time_us; val = get_unaligned_be32(&power->vdn.update_tag) * occ->powr_sample_time_us; Addresses-Coverity-ID: 1442357 ("Unintentional integer overflow") Addresses-Coverity-ID: 1442476 ("Unintentional integer overflow") Addresses-Coverity-ID: 1442508 ("Unintentional integer overflow") Fixes: ff692d80b2e2 ("hwmon (occ): Add sensor types and versions") Cc: stable@vger.kernel.org Signed-off-by: Gustavo A. R. Silva Reviewed-by: Eddie James Signed-off-by: Guenter Roeck

hwmon (occ): Add sysfs attributes for additional OCC data

2018-12-16T23:13:10Z

The OCC provides a variety of additional information about the state of the host processor, such as throttling, error conditions, and the number of OCCs detected in the system. This information is essential to service processor applications such as fan control and host management. Therefore, export this data in the form of sysfs attributes attached to the platform device (to which the hwmon device is also attached). Signed-off-by: Eddie James Signed-off-by: Guenter Roeck

hwmon (occ): Add sensor attributes and register hwmon device

2018-12-16T23:13:09Z

Setup the sensor attributes for every OCC sensor found by the first poll response. Register the attributes with hwmon. Signed-off-by: Eddie James Signed-off-by: Guenter Roeck

hwmon (occ): Add sensor types and versions

2018-12-16T23:13:09Z

Add structures to define all sensor types and versions. Add sysfs show and store functions for each sensor type. Add a method to construct the "set user power cap" command and send it to the OCC. Add rate limit to polling the OCC (in case user-space reads our hwmon entries rapidly). Signed-off-by: Eddie James Signed-off-by: Guenter Roeck

hwmon (occ): Parse OCC poll response

2018-12-16T23:13:08Z

Add method to parse the response from the OCC poll command. This only needs to be done during probe(), since the OCC shouldn't change the number or format of sensors while it's running. The parsed response allows quick access to sensor data, as well as information on the number and version of sensors, which we need to instantiate hwmon attributes. Signed-off-by: Eddie James Signed-off-by: Guenter Roeck

hwmon (occ): Add command transport method for P8 and P9

2018-12-16T23:13:08Z

For the P8 OCC, add the procedure to send a command to the OCC over I2C bus. This involves writing the OCC command registers with serial communication operations (SCOMs) interpreted by the I2C slave. For the P9 OCC, add a procedure to use the OCC in-kernel API to send a command to the OCC through the SBE. Signed-off-by: Eddie James Signed-off-by: Guenter Roeck

hwmon: Add On-Chip Controller (OCC) hwmon driver

2018-12-16T23:13:05Z

The OCC is a device embedded on a POWER processor that collects and aggregates sensor data from the processor and system. The OCC can provide the raw sensor data as well as perform thermal and power management on the system. This driver provides a hwmon interface to the OCC from a service processor (e.g. a BMC). The driver supports both POWER8 and POWER9 OCCs. Communications with the POWER8 OCC are established over standard I2C bus. The driver communicates with the POWER9 OCC through the FSI-based OCC driver, which handles the lower-level communication details. This patch lays out the structure of the OCC hwmon driver. There are two platform drivers, one each for P8 and P9 OCCs. These are probed through the I2C tree and the FSI-based OCC driver, respectively. The patch also defines the first common structures and methods between the two OCC versions. Signed-off-by: Eddie James [groeck: Fix up SPDX license identifier] Signed-off-by: Guenter Roeck