kernel/drivers/gpu/nova-core/regs.rs, branch linux-6.19.y

gpu: nova-core: provide a clear error report for unsupported GPUs

2025-11-15T14:11:28Z

Pass in a PCI device to Spec::new(), and provide a Display implementation for boot42, in order to provide a clear, concise report of what happened: the driver read NV_PMC_BOOT42, and found that the GPU is not supported. For very old GPUs (older than Fermi), the driver still returns ENODEV, but it does so without a driver-specific dmesg report. That is exactly appropriate, because if such a GPU is installed, it can only be supported by Nouveau. And if so, the user is not helped by additional error messages from Nova. Here's the full dmesg output for a Blackwell (not yet supported) GPU: NovaCore 0000:01:00.0: Probe Nova Core GPU driver. NovaCore 0000:01:00.0: Unsupported chipset: boot42 = 0x1b2a1000 (architecture 0x1b, implementation 0x2) NovaCore 0000:01:00.0: probe with driver NovaCore failed with error -524 Cc: Alexandre Courbot Cc: Danilo Krummrich Cc: Timur Tabi Cc: Joel Fernandes Signed-off-by: John Hubbard [acourbot@nvidia.com: fix commit log with ENODEV (not ENOTSUPP) error code for unsupported GPUs.] Signed-off-by: Alexandre Courbot Message-ID: <20251115010923.1192144-5-jhubbard@nvidia.com>

gpu: nova-core: add boot42 support for next-gen GPUs

2025-11-15T14:11:27Z

NVIDIA GPUs are moving away from using NV_PMC_BOOT_0 to contain architecture and revision details, and will instead use NV_PMC_BOOT_42 in the future. NV_PMC_BOOT_0 will contain a specific set of values that will mean "go read NV_PMC_BOOT_42 instead". Change the selection logic in Nova so that it will claim Turing and later GPUs. This will work for the foreseeable future, without any further code changes here, because all NVIDIA GPUs are considered, from the oldest supported on Linux (NV04), through the future GPUs. Add some comment documentation to explain, chronologically, how boot0 and boot42 change with the GPU eras, and how that affects the selection logic. Cc: Alexandre Courbot Cc: Danilo Krummrich Cc: Timur Tabi Reviewed-by: Joel Fernandes Signed-off-by: John Hubbard [acourbot@nvidia.com: remove unneeded `From for Revision` implementation.] Signed-off-by: Alexandre Courbot Message-ID: <20251115010923.1192144-4-jhubbard@nvidia.com>

gpu: nova-core: gsp: Add support for checking if GSP reloaded

2025-11-15T11:08:49Z

During the sequencer process, we need to check if GSP was successfully reloaded. Add functionality to check for the same. Reviewed-by: Lyude Paul Signed-off-by: Joel Fernandes Signed-off-by: Alexandre Courbot Message-ID: <20251114195552.739371-6-joelagnelf@nvidia.com>

gpu: nova-core: falcon: Add support to write firmware version

2025-11-14T11:25:57Z

This will be needed by both the GSP boot code as well as GSP resume code in the sequencer. Reviewed-by: Lyude Paul Signed-off-by: Joel Fernandes Signed-off-by: Alexandre Courbot Message-ID: <20251110-gsp_boot-v9-14-8ae4058e3c0e@nvidia.com>

gpu: nova-core: falcon: Add support to check if RISC-V is active

2025-11-14T11:25:57Z

Add definition for RISCV_CPUCTL register and use it in a new falcon API to check if the RISC-V core of a Falcon is active. It is required by the sequencer to know if the GSP's RISCV processor is active. Reviewed-by: Lyude Paul Signed-off-by: Joel Fernandes Signed-off-by: Alexandre Courbot Message-ID: <20251110-gsp_boot-v9-13-8ae4058e3c0e@nvidia.com>

gpu: nova-core: gsp: Add GSP command queue bindings and handling

2025-11-14T11:25:57Z

This commit introduces core infrastructure for handling GSP command and message queues in the nova-core driver. The command queue system enables bidirectional communication between the host driver and GSP firmware through a remote message passing interface. The interface is based on passing serialised data structures over a ring buffer with separate transmit and receive queues. Commands are sent by writing to the CPU transmit queue and waiting for completion via the receive queue. To ensure safety mutable or immutable (depending on whether it is a send or receive operation) references are taken on the command queue when allocating the message to write/read to. This ensures message memory remains valid and the command queue can't be mutated whilst an operation is in progress. Currently this is only used by the probe() routine and therefore can only used by a single thread of execution. Locking to enable safe access from multiple threads will be introduced in a future series when that becomes necessary. Signed-off-by: Alistair Popple Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Message-ID: <20251110-gsp_boot-v9-9-8ae4058e3c0e@nvidia.com>

gpu: nova-core: replace use of `as` with functions from `num`

2025-11-07T23:22:45Z

Use the newly-introduced `num` module to replace the use of `as` wherever it is safe to do. This ensures that a given conversion cannot lose data if its source or destination type ever changes. Acked-by: Danilo Krummrich [acourbot@nvidia.com: fix merge conflicts after rebase.] Signed-off-by: Alexandre Courbot Message-ID: <20251029-nova-as-v3-5-6a30c7333ad9@nvidia.com>

gpu: nova-core: apply the one "use" item per line policy

2025-11-07T14:10:44Z

As per [1], we need one "use" item per line, in order to reduce merge conflicts. Furthermore, we need a trailing ", //" in order to tell rustfmt(1) to leave it alone. This does that for the entire nova-core driver. [1] https://docs.kernel.org/rust/coding-guidelines.html#imports Acked-by: Danilo Krummrich Signed-off-by: John Hubbard [acourbot@nvidia.com: remove imports already in prelude as pointed out by Danilo.] [acourbot@nvidia.com: remove a few unneeded trailing `//`.] Signed-off-by: Alexandre Courbot Message-ID: <20251107021006.434109-1-jhubbard@nvidia.com>

gpu: nova-core: register: add support for relative array registers

2025-08-15T03:02:56Z

Add support for declaring arrays of registers available from a variable base. This is effectively a combination of the relative and array registers features. nova-core does not make much use of this yet, but it will become helpful to have for GSP boot. Reviewed-by: Lyude Paul Link: https://lore.kernel.org/r/20250718-nova-regs-v2-19-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: falcon: use register arrays for FUSE registers

2025-08-15T03:02:56Z

FUSE registers are an array of 16 consecutive registers. Use the newly available register array feature to define them properly and improve the code using them. Reviewed-by: Lyude Paul Link: https://lore.kernel.org/r/20250718-nova-regs-v2-18-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot