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<title>kernel/drivers/gpu/nova-core/falcon.rs, branch linux-6.19.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.19.y</id>
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<updated>2026-02-26T23:01:00Z</updated>
<entry>
<title>gpu: nova-core: check for overflow to DMATRFBASE1</title>
<updated>2026-02-26T23:01:00Z</updated>
<author>
<name>Timur Tabi</name>
<email>ttabi@nvidia.com</email>
</author>
<published>2026-01-07T20:16:46Z</published>
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<id>urn:sha1:f2c3c93799df3998a0a16bf5b7989625dcf56bd3</id>
<content type='text'>
[ Upstream commit 5cf76277cdec872aef9ff2e9008ae129bb303787 ]

The NV_PFALCON_FALCON_DMATRFBASE/1 register pair supports DMA addresses
up to 49 bits only, but the write to DMATRFBASE1 could exceed that.
To mitigate, check first that the DMA address will fit.

Reviewed-by: John Hubbard &lt;jhubbard@nvidia.com&gt;
Reviewed-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Fixes: 69f5cd67ce41 ("gpu: nova-core: add falcon register definitions and base code")
Signed-off-by: Timur Tabi &lt;ttabi@nvidia.com&gt;
Link: https://patch.msgid.link/20260107201647.2490140-1-ttabi@nvidia.com
[ Import ::kernel::dma::DmaMask. - Danilo ]
Signed-off-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: falcon: Move dma_reset functionality into helper</title>
<updated>2025-11-15T11:08:49Z</updated>
<author>
<name>Joel Fernandes</name>
<email>joelagnelf@nvidia.com</email>
</author>
<published>2025-11-14T19:55:43Z</published>
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<id>urn:sha1:0f2c8e278e9c6219c080d1e016cd72b07d50e444</id>
<content type='text'>
Move dma_reset so we can use it for the upcoming sequencer
functionality.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-5-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: falcon: Move mbox functionalities into helper</title>
<updated>2025-11-15T11:08:49Z</updated>
<author>
<name>Joel Fernandes</name>
<email>joelagnelf@nvidia.com</email>
</author>
<published>2025-11-14T19:55:42Z</published>
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<id>urn:sha1:4f7656f79901dc00481b102c821705c992f7b982</id>
<content type='text'>
Move falcon reading/writing to mbox functionality into helper so we can
use it from the sequencer resume flow.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
[acourbot@nvidia.com: make write/read mailbox methods unfallible.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-4-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: falcon: Move start functionality into separate helper</title>
<updated>2025-11-15T08:28:03Z</updated>
<author>
<name>Joel Fernandes</name>
<email>joelagnelf@nvidia.com</email>
</author>
<published>2025-11-14T19:55:41Z</published>
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<id>urn:sha1:c5c0cfa67aa429b171676c6162f123adecb3a5ec</id>
<content type='text'>
Move start functionality into a separate helper so we can use it from
the sequencer.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-3-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: falcon: Move waiting until halted to a helper</title>
<updated>2025-11-15T08:28:03Z</updated>
<author>
<name>Joel Fernandes</name>
<email>joelagnelf@nvidia.com</email>
</author>
<published>2025-11-14T19:55:40Z</published>
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<id>urn:sha1:2d981773e14c1d7fc8f8e19a19d306d8372db571</id>
<content type='text'>
Move the "waiting until halted" functionality into a helper so that we
can use it in the sequencer, which is a separate sequencer operation.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251114195552.739371-2-joelagnelf@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: gsp: Boot GSP</title>
<updated>2025-11-14T11:25:57Z</updated>
<author>
<name>Alistair Popple</name>
<email>apopple@nvidia.com</email>
</author>
<published>2025-11-10T13:34:23Z</published>
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<id>urn:sha1:5949d419c193ce8e285acfbaafad88efe87f9dfa</id>
<content type='text'>
Boot the GSP to the RISC-V active state. Completing the boot requires
running the CPU sequencer which will be added in a future commit.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Alistair Popple &lt;apopple@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251110-gsp_boot-v9-15-8ae4058e3c0e@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: falcon: Add support to write firmware version</title>
<updated>2025-11-14T11:25:57Z</updated>
<author>
<name>Joel Fernandes</name>
<email>joelagnelf@nvidia.com</email>
</author>
<published>2025-11-10T13:34:22Z</published>
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<id>urn:sha1:945c1eee7dbeb0dcafc9d151eaa46a4273d386fa</id>
<content type='text'>
This will be needed by both the GSP boot code as well as GSP resume code
in the sequencer.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251110-gsp_boot-v9-14-8ae4058e3c0e@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: falcon: Add support to check if RISC-V is active</title>
<updated>2025-11-14T11:25:57Z</updated>
<author>
<name>Joel Fernandes</name>
<email>joelagnelf@nvidia.com</email>
</author>
<published>2025-11-10T13:34:21Z</published>
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<id>urn:sha1:bb58d1aee6081dba5f64eacf48993c077e99dd4a</id>
<content type='text'>
Add definition for RISCV_CPUCTL register and use it in a new falcon API
to check if the RISC-V core of a Falcon is active. It is required by
the sequencer to know if the GSP's RISCV processor is active.

Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Signed-off-by: Joel Fernandes &lt;joelagnelf@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251110-gsp_boot-v9-13-8ae4058e3c0e@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: justify remaining uses of `as`</title>
<updated>2025-11-07T23:22:51Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2025-10-26T13:06:54Z</published>
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<id>urn:sha1:80b3dc0a5a2e51fb2b8f3406f5ee20ad4a652316</id>
<content type='text'>
There are a few remaining cases where we *do* want to use `as`,
because we specifically want to strip the data that does not fit into
the destination type. Comment these uses to clear confusion about the
intent.

Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
[acourbot@nvidia.com: fix merge conflicts after rebase.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251029-nova-as-v3-6-6a30c7333ad9@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: replace use of `as` with functions from `num`</title>
<updated>2025-11-07T23:22:45Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2025-10-27T14:12:31Z</published>
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<id>urn:sha1:84e2b401bcc551e7c2e1a995f90cce421bce5bfd</id>
<content type='text'>
Use the newly-introduced `num` module to replace the use of `as`
wherever it is safe to do. This ensures that a given conversion cannot
lose data if its source or destination type ever changes.

Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
[acourbot@nvidia.com: fix merge conflicts after rebase.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Message-ID: &lt;20251029-nova-as-v3-5-6a30c7333ad9@nvidia.com&gt;
</content>
</entry>
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