Hosts the 0x221E linux distro kernel. https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.19.y 2025-10-25T04:16:31Z 2025-10-25T04:16:31Z Alexandre Courbot acourbot@nvidia.com 2025-10-22T10:50:58Z urn:sha1:ca16b15e78f4dee1631c0a68693f5e7d9b3bb3ec Using this operand can produce invalid values. It also doesn't bring any benefit as one can use the builder pattern to assemble a new value. Reported-by: Edwin Peer <epeer@nvidia.com> Link: https://lore.kernel.org/rust-for-linux/F3853912-2C1C-4F9B-89B0-3168689F35B3@nvidia.com/ Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251022-nova-bitfield-v1-3-73bc0988667b@nvidia.com> 2025-10-25T04:16:31Z Alexandre Courbot acourbot@nvidia.com 2025-10-22T10:50:57Z urn:sha1:e6b8932b9374bd0591bb4dda3eb3e4f1cc50655e The shift is more easily expressed by the index of the lowest bit of the field. Reported-by: Edwin Peer <epeer@nvidia.com> Link: https://lore.kernel.org/rust-for-linux/F3853912-2C1C-4F9B-89B0-3168689F35B3@nvidia.com/ Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251022-nova-bitfield-v1-2-73bc0988667b@nvidia.com> 2025-10-25T04:16:31Z Alexandre Courbot acourbot@nvidia.com 2025-10-22T10:50:56Z urn:sha1:fa08ec789f81425c3722fd2c6df825e06c810b43 This condition was uselessly convoluted. Reported-by: Edwin Peer <epeer@nvidia.com> Link: https://lore.kernel.org/rust-for-linux/F3853912-2C1C-4F9B-89B0-3168689F35B3@nvidia.com/ Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251022-nova-bitfield-v1-1-73bc0988667b@nvidia.com> 2025-10-21T13:40:00Z Joel Fernandes joelagnelf@nvidia.com 2025-10-16T15:13:23Z urn:sha1:77ed4376d7c5de8be1f2612d6b4777077fb5fdb2 Add support for custom visibility to allow for users to control visibility of the structure and helpers. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev> Reviewed-by: Edwin Peer <epeer@nvidia.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [acourbot@nvidia.com: fix long lines warnings and typo in commit message.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251016151323.1201196-5-joelagnelf@nvidia.com> 2025-10-21T13:39:44Z Joel Fernandes joelagnelf@nvidia.com 2025-10-16T15:13:22Z urn:sha1:7cabacb1aad647931980f63fa18292ad3f859544 Previously, bitfields were hardcoded to use u32 as the underlying storage type. Add support for different storage types (u8, u16, u32, u64) to the bitfield macro. New syntax is: struct Name(<type ex., u32>) { ... } Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev> Reviewed-by: Edwin Peer <epeer@nvidia.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [acourbot@nvidia.com: fix long lines warnings.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251016151323.1201196-4-joelagnelf@nvidia.com> 2025-10-21T13:38:57Z Joel Fernandes joelagnelf@nvidia.com 2025-10-16T15:13:21Z urn:sha1:71ea85be25b4f54a53ec03d5deaed52f5ee65da8 Move the bitfield-specific code from the register macro into a new macro called bitfield. This will be used to define structs with bitfields, similar to C language. Reviewed-by: Elle Rhumsaa <elle@weathered-steel.dev> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Edwin Peer <epeer@nvidia.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251016151323.1201196-3-joelagnelf@nvidia.com>